ORION5X_BRIDGE_VIRT_BASE

11

#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)

13

#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)

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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)

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#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)

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#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)

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#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)

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#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)

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#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)

9

#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)

263

orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,