OP___assert
OP___assert(elem);
OP___assert(src);
OP___assert(dest);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb->desc->size > 0);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(elem);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc);
OP___assert(cb_desc->size > 0);
OP___assert(desc);
OP___assert(ID < N_GPIO_ID);
OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
OP___assert(ID < N_GPIO_ID);
OP___assert(GPIO_BASE[ID] != (hrt_address) - 1);
OP___assert(ID == IRQ0_ID);
OP___assert(IRQ_BASE[ID] != (hrt_address)-1);
OP___assert(irq_id < N_IRQ_SW_CHANNEL_ID);
OP___assert(ID == TIMED_CTRL0_ID);
OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1);
OP___assert(SP_ID < N_SP_ID);
OP___assert(SP_DMEM_BASE[SP_ID] != (hrt_address)-1);
OP___assert(GPIO_ID < N_GPIO_ID);
OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1);
OP___assert(ID < N_TIMED_CTRL_ID);
OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address) - 1);
OP___assert(nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT);
OP___assert(port < N_CSI_PORTS);
OP___assert(idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT);