OP_MASK
#define OPTO_MASK (OP_MASK | TO_MASK)
#define DRA_MASK (OP_MASK | RA_MASK)
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
u8 op = amsg->cmd & OP_MASK;
if ((last_cmd & OP_MASK) == TALK) {
} else if ((req->data[1] & OP_MASK) == TALK) {