arch/parisc/kernel/unaligned.c

36

#define OPCODE1_MASK OPCODE1(0x3f,1,0xf)

arch/parisc/kernel/unaligned.c

42

#define OPCODE_LDH_I OPCODE1(0x03,0,0x1)

arch/parisc/kernel/unaligned.c

43

#define OPCODE_LDW_I OPCODE1(0x03,0,0x2)

arch/parisc/kernel/unaligned.c

44

#define OPCODE_LDD_I OPCODE1(0x03,0,0x3)

arch/parisc/kernel/unaligned.c

45

#define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)

arch/parisc/kernel/unaligned.c

46

#define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)

arch/parisc/kernel/unaligned.c

47

#define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)

arch/parisc/kernel/unaligned.c

48

#define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)

arch/parisc/kernel/unaligned.c

50

#define OPCODE_LDH_S OPCODE1(0x03,1,0x1)

arch/parisc/kernel/unaligned.c

51

#define OPCODE_LDW_S OPCODE1(0x03,1,0x2)

arch/parisc/kernel/unaligned.c

52

#define OPCODE_LDD_S OPCODE1(0x03,1,0x3)

arch/parisc/kernel/unaligned.c

53

#define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)

arch/parisc/kernel/unaligned.c

54

#define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)

arch/parisc/kernel/unaligned.c

55

#define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)

arch/parisc/kernel/unaligned.c

56

#define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)

arch/parisc/kernel/unaligned.c

58

#define OPCODE_STH OPCODE1(0x03,1,0x9)

arch/parisc/kernel/unaligned.c

59

#define OPCODE_STW OPCODE1(0x03,1,0xa)

arch/parisc/kernel/unaligned.c

60

#define OPCODE_STD OPCODE1(0x03,1,0xb)

arch/parisc/kernel/unaligned.c

63

#define OPCODE_STWA OPCODE1(0x03,1,0xe)

arch/parisc/kernel/unaligned.c

64

#define OPCODE_STDA OPCODE1(0x03,1,0xf)

arch/parisc/kernel/unaligned.c

66

#define OPCODE_FLDWX OPCODE1(0x09,0,0x0)

arch/parisc/kernel/unaligned.c

67

#define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)

arch/parisc/kernel/unaligned.c

68

#define OPCODE_FSTWX OPCODE1(0x09,0,0x8)

arch/parisc/kernel/unaligned.c

69

#define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)

arch/parisc/kernel/unaligned.c

70

#define OPCODE_FLDWS OPCODE1(0x09,1,0x0)

arch/parisc/kernel/unaligned.c

71

#define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)

arch/parisc/kernel/unaligned.c

72

#define OPCODE_FSTWS OPCODE1(0x09,1,0x8)

arch/parisc/kernel/unaligned.c

73

#define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)

arch/parisc/kernel/unaligned.c

74

#define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)

arch/parisc/kernel/unaligned.c

75

#define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)

arch/parisc/kernel/unaligned.c

76

#define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)

arch/parisc/kernel/unaligned.c

77

#define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)

arch/x86/kernel/uprobes.c

1404

u8 opc1 = OPCODE1(insn);

arch/x86/kernel/uprobes.c

1455

u8 opc1 = OPCODE1(insn), reg_offset = 0;

arch/x86/kernel/uprobes.c

1565

switch (OPCODE1(&insn)) {

arch/x86/kernel/uprobes.c

301

if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))