arch/arm/include/asm/hw_breakpoint.h

110

#define ARM_DBG_READ(N, M, OP2, VAL) do {\

arch/arm/include/asm/hw_breakpoint.h

111

asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\

arch/arm/include/asm/hw_breakpoint.h

114

#define ARM_DBG_WRITE(N, M, OP2, VAL) do {\

arch/arm/include/asm/hw_breakpoint.h

115

asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\

arch/arm/kernel/hw_breakpoint.c

49

#define READ_WB_REG_CASE(OP2, M, VAL) \

arch/arm/kernel/hw_breakpoint.c

50

case ((OP2 << 4) + M): \

arch/arm/kernel/hw_breakpoint.c

51

ARM_DBG_READ(c0, c ## M, OP2, VAL); \

arch/arm/kernel/hw_breakpoint.c

54

#define WRITE_WB_REG_CASE(OP2, M, VAL) \

arch/arm/kernel/hw_breakpoint.c

55

case ((OP2 << 4) + M): \

arch/arm/kernel/hw_breakpoint.c

56

ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \

arch/arm/kernel/hw_breakpoint.c

59

#define GEN_READ_WB_REG_CASES(OP2, VAL) \

arch/arm/kernel/hw_breakpoint.c

60

READ_WB_REG_CASE(OP2, 0, VAL); \

arch/arm/kernel/hw_breakpoint.c

61

READ_WB_REG_CASE(OP2, 1, VAL); \

arch/arm/kernel/hw_breakpoint.c

62

READ_WB_REG_CASE(OP2, 2, VAL); \

arch/arm/kernel/hw_breakpoint.c

63

READ_WB_REG_CASE(OP2, 3, VAL); \

arch/arm/kernel/hw_breakpoint.c

64

READ_WB_REG_CASE(OP2, 4, VAL); \

arch/arm/kernel/hw_breakpoint.c

65

READ_WB_REG_CASE(OP2, 5, VAL); \

arch/arm/kernel/hw_breakpoint.c

66

READ_WB_REG_CASE(OP2, 6, VAL); \

arch/arm/kernel/hw_breakpoint.c

67

READ_WB_REG_CASE(OP2, 7, VAL); \

arch/arm/kernel/hw_breakpoint.c

68

READ_WB_REG_CASE(OP2, 8, VAL); \

arch/arm/kernel/hw_breakpoint.c

69

READ_WB_REG_CASE(OP2, 9, VAL); \

arch/arm/kernel/hw_breakpoint.c

70

READ_WB_REG_CASE(OP2, 10, VAL); \

arch/arm/kernel/hw_breakpoint.c

71

READ_WB_REG_CASE(OP2, 11, VAL); \

arch/arm/kernel/hw_breakpoint.c

72

READ_WB_REG_CASE(OP2, 12, VAL); \

arch/arm/kernel/hw_breakpoint.c

73

READ_WB_REG_CASE(OP2, 13, VAL); \

arch/arm/kernel/hw_breakpoint.c

74

READ_WB_REG_CASE(OP2, 14, VAL); \

arch/arm/kernel/hw_breakpoint.c

75

READ_WB_REG_CASE(OP2, 15, VAL)

arch/arm/kernel/hw_breakpoint.c

77

#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \

arch/arm/kernel/hw_breakpoint.c

78

WRITE_WB_REG_CASE(OP2, 0, VAL); \

arch/arm/kernel/hw_breakpoint.c

79

WRITE_WB_REG_CASE(OP2, 1, VAL); \

arch/arm/kernel/hw_breakpoint.c

80

WRITE_WB_REG_CASE(OP2, 2, VAL); \

arch/arm/kernel/hw_breakpoint.c

81

WRITE_WB_REG_CASE(OP2, 3, VAL); \

arch/arm/kernel/hw_breakpoint.c

82

WRITE_WB_REG_CASE(OP2, 4, VAL); \

arch/arm/kernel/hw_breakpoint.c

83

WRITE_WB_REG_CASE(OP2, 5, VAL); \

arch/arm/kernel/hw_breakpoint.c

84

WRITE_WB_REG_CASE(OP2, 6, VAL); \

arch/arm/kernel/hw_breakpoint.c

85

WRITE_WB_REG_CASE(OP2, 7, VAL); \

arch/arm/kernel/hw_breakpoint.c

86

WRITE_WB_REG_CASE(OP2, 8, VAL); \

arch/arm/kernel/hw_breakpoint.c

87

WRITE_WB_REG_CASE(OP2, 9, VAL); \

arch/arm/kernel/hw_breakpoint.c

88

WRITE_WB_REG_CASE(OP2, 10, VAL); \

arch/arm/kernel/hw_breakpoint.c

89

WRITE_WB_REG_CASE(OP2, 11, VAL); \

arch/arm/kernel/hw_breakpoint.c

90

WRITE_WB_REG_CASE(OP2, 12, VAL); \

arch/arm/kernel/hw_breakpoint.c

91

WRITE_WB_REG_CASE(OP2, 13, VAL); \

arch/arm/kernel/hw_breakpoint.c

92

WRITE_WB_REG_CASE(OP2, 14, VAL); \

arch/arm/kernel/hw_breakpoint.c

93

WRITE_WB_REG_CASE(OP2, 15, VAL)

arch/arm64/include/uapi/asm/kvm.h

253

ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

arch/sparc/net/bpf_jit_comp_32.c

33

#define F2(X, Y) (OP(X) | OP2(Y))

arch/sparc/net/bpf_jit_comp_64.c

63

#define F2(X, Y) (OP(X) | OP2(Y))

fs/afs/internal.h

1903

#define ASSERTRANGE(L, OP1, N, OP2, H) \

fs/afs/internal.h

1905

if (unlikely(!((L) OP1 (N)) || !((N) OP2 (H)))) { \

fs/afs/internal.h

1908

printk(KERN_ERR "%lu "#OP1" %lu "#OP2" %lu is false\n", \

fs/afs/internal.h

1911

printk(KERN_ERR "0x%lx "#OP1" 0x%lx "#OP2" 0x%lx is false\n", \

fs/afs/internal.h

1950

#define ASSERTRANGE(L, OP1, N, OP2, H) \

tools/arch/arm64/include/uapi/asm/kvm.h

253

ARM64_SYS_REG_SHIFT_MASK(op2, OP2))