arch/arm/mach-omap1/ams-delta-fiq.h

32

#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE

arch/arm/mach-omap1/hardware.h

130

#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)

arch/arm/mach-omap1/hardware.h

131

#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)

arch/arm/mach-omap1/hardware.h

132

#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)

arch/arm/mach-omap1/hardware.h

133

#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)

arch/arm/mach-omap1/hardware.h

134

#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)

arch/arm/mach-omap1/hardware.h

135

#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)

arch/arm/mach-omap1/hardware.h

136

#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)

arch/arm/mach-omap1/irq.c

117

{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },

arch/arm/mach-omap1/irq.c

121

{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },

arch/arm/mach-omap1/irq.c

129

{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },

arch/arm/mach-omap1/irq.c

130

{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },

arch/arm/mach-omap1/irq.c

131

{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },