arch/arm/mach-omap1/ams-delta-fiq.c

200

val = omap_readl(OMAP_IH1_BASE + offset) | 1;

arch/arm/mach-omap1/ams-delta-fiq.c

201

omap_writel(val, OMAP_IH1_BASE + offset);

arch/arm/mach-omap1/ams-delta-fiq.h

30

#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE

arch/arm/mach-omap1/hardware.h

122

#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)

arch/arm/mach-omap1/hardware.h

123

#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)

arch/arm/mach-omap1/hardware.h

124

#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)

arch/arm/mach-omap1/hardware.h

125

#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)

arch/arm/mach-omap1/hardware.h

126

#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)

arch/arm/mach-omap1/hardware.h

127

#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)

arch/arm/mach-omap1/hardware.h

128

#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)

arch/arm/mach-omap1/irq.c

116

{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },

arch/arm/mach-omap1/irq.c

120

{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },

arch/arm/mach-omap1/irq.c

128

{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },