arch/arm/mach-omap2/clockdomains44xx_data.c

284

.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,

arch/arm/mach-omap2/omap-mpuss-lowpower.c

168

reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,

arch/arm/mach-omap2/omap-mpuss-lowpower.c

170

omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,

arch/arm/mach-omap2/powerdomains44xx_data.c

170

.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,

arch/arm/mach-omap2/prcm_mpu44xx.h

80

#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)

arch/arm/mach-omap2/prcm_mpu44xx.h

82

#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)

arch/arm/mach-omap2/prcm_mpu44xx.h

84

#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)

arch/arm/mach-omap2/prcm_mpu44xx.h

86

#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)

arch/arm/mach-omap2/prcm_mpu44xx.h

88

#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)

arch/arm/mach-omap2/prcm_mpu44xx.h

90

#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)

arch/arm/mach-omap2/prcm_mpu44xx.h

92

#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)