arch/arm/mach-omap2/clockdomains44xx_data.c

275

.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,

arch/arm/mach-omap2/omap-mpuss-lowpower.c

173

reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,

arch/arm/mach-omap2/omap-mpuss-lowpower.c

175

omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,

arch/arm/mach-omap2/powerdomains44xx_data.c

153

.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,

arch/arm/mach-omap2/prcm_mpu44xx.h

64

#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)

arch/arm/mach-omap2/prcm_mpu44xx.h

66

#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)

arch/arm/mach-omap2/prcm_mpu44xx.h

68

#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)

arch/arm/mach-omap2/prcm_mpu44xx.h

70

#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)

arch/arm/mach-omap2/prcm_mpu44xx.h

72

#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)

arch/arm/mach-omap2/prcm_mpu44xx.h

74

#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)

arch/arm/mach-omap2/prcm_mpu44xx.h

76

#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)