arch/arm/mach-omap2/cm3xxx.c

389

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);

arch/arm/mach-omap2/cm3xxx.c

430

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);

arch/arm/mach-omap2/cm3xxx.c

448

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);

arch/arm/mach-omap2/cm3xxx.c

468

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);

arch/arm/mach-omap2/cm3xxx.c

487

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);

arch/arm/mach-omap2/cm3xxx.c

498

omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);

arch/arm/mach-omap2/cm3xxx.c

521

omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/cm3xxx.c

559

omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/cm3xxx.c

576

omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/cm3xxx.c

596

omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/cm3xxx.c

614

omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/cm3xxx.c

624

omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

458

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

474

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

511

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

550

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

568

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

587

.module_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/powerdomains3xxx_data.c

153

.prcm_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/powerdomains3xxx_data.c

168

.prcm_offs = OMAP3430_DSS_MOD,

arch/arm/mach-omap2/prm3xxx.c

315

OMAP3430_DSS_MOD, PM_WKEN);

arch/arm/mach-omap2/prm3xxx.c

366

omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);