NVWriteVgaCrtc
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX,
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
NVWriteVgaCrtc(dev, head ^ 1,
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);
NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49,
NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB :