Symbol: NVReadRAMDAC
drivers/gpu/drm/nouveau/dispnv04/crtc.c
726
uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
drivers/gpu/drm/nouveau/dispnv04/dac.c
160
saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/dac.c
178
saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/dac.c
260
saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
281
saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
301
temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
306
temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/dac.c
311
sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
313
sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
315
temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/dac.c
399
otherdac = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset);
drivers/gpu/drm/nouveau/dispnv04/dac.c
434
uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off);
drivers/gpu/drm/nouveau/dispnv04/dac.c
481
nv_encoder->restore.output = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
drivers/gpu/drm/nouveau/dispnv04/dfp.c
465
NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/dfp.c
557
nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
drivers/gpu/drm/nouveau/dispnv04/dfp.c
65
return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
drivers/gpu/drm/nouveau/dispnv04/dfp.c
97
if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
drivers/gpu/drm/nouveau/dispnv04/hw.c
188
uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
drivers/gpu/drm/nouveau/dispnv04/hw.c
401
regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
drivers/gpu/drm/nouveau/dispnv04/hw.c
404
state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
drivers/gpu/drm/nouveau/dispnv04/hw.c
406
state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
drivers/gpu/drm/nouveau/dispnv04/hw.c
408
regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
drivers/gpu/drm/nouveau/dispnv04/hw.c
410
regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/hw.c
413
regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
drivers/gpu/drm/nouveau/dispnv04/hw.c
415
regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
drivers/gpu/drm/nouveau/dispnv04/hw.c
417
regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
drivers/gpu/drm/nouveau/dispnv04/hw.c
418
regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
drivers/gpu/drm/nouveau/dispnv04/hw.c
419
regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
drivers/gpu/drm/nouveau/dispnv04/hw.c
420
regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
drivers/gpu/drm/nouveau/dispnv04/hw.c
421
regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
drivers/gpu/drm/nouveau/dispnv04/hw.c
422
regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
drivers/gpu/drm/nouveau/dispnv04/hw.c
423
regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
drivers/gpu/drm/nouveau/dispnv04/hw.c
424
regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
drivers/gpu/drm/nouveau/dispnv04/hw.c
428
regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
drivers/gpu/drm/nouveau/dispnv04/hw.c
429
regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
drivers/gpu/drm/nouveau/dispnv04/hw.c
433
regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
drivers/gpu/drm/nouveau/dispnv04/hw.c
435
regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
drivers/gpu/drm/nouveau/dispnv04/hw.c
436
regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
drivers/gpu/drm/nouveau/dispnv04/hw.c
440
regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/hw.c
441
regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
drivers/gpu/drm/nouveau/dispnv04/hw.c
448
regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
drivers/gpu/drm/nouveau/dispnv04/hw.c
449
regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
drivers/gpu/drm/nouveau/dispnv04/hw.c
451
regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
drivers/gpu/drm/nouveau/dispnv04/hw.c
454
regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
drivers/gpu/drm/nouveau/dispnv04/hw.c
457
regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
drivers/gpu/drm/nouveau/dispnv04/hw.c
458
regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
drivers/gpu/drm/nouveau/dispnv04/hw.c
459
regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
drivers/gpu/drm/nouveau/dispnv04/hw.c
462
regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
drivers/gpu/drm/nouveau/dispnv04/hw.c
702
reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
drivers/gpu/drm/nouveau/dispnv04/hw.h
106
return NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8);
drivers/gpu/drm/nouveau/dispnv04/hw.h
348
uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
105
sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
111
sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
443
dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
619
NVReadRAMDAC(dev, 0,
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
62
dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
68
fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
69
fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
70
fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
71
fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
72
test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
73
ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
74
ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
75
ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
drivers/gpu/drm/nouveau/nouveau_bios.c
249
sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
drivers/gpu/drm/nouveau/nouveau_bios.c
673
sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;