NvU32
typedef NvU32 NvHandle;
typedef NvU32 NV_STATUS;
NvU32 frtsSysmemSize;
NvU32 frtsVidmemSize;
NvU32 hash384[12];
NvU32 publicKey[96];
NvU32 signature[96];
NvU32 taskId;
NvU32 commandNvdmType;
NvU32 errorCode;
NvU32 hClass;
NvU32 status;
NvU32 paramsSize;
NvU32 flags;
NvU32 version;
NvU32 engineType;
NvU32 processID;
NvU32 cmd;
NvU32 status;
NvU32 paramsSize;
NvU32 flags;
NvU32 deviceId;
NvU32 subDeviceId;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupported;
NvU32 instMemAddrSpace;
NvU32 instMemCpuCacheAttr;
NvU32 plugDisplayMask;
NvU32 unplugDisplayMask;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 flags;
NvU32 displayMask;
NvU32 retryTimeMs;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 flags2;
NvU32 feHwSysCap;
NvU32 windowPresentMask;
NvU32 subDeviceInstance;
NvU32 head;
NvU32 flags;
NvU32 displayId;
typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
NvU32 numHeads;
NvU32 displayMask;
NvU32 sorType;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 slaveDisplayId;
NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
NvU32 flags;
NvU32 i2cPort;
NvU32 internalDispActiveMask;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 brightness;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 numELDSize;
NvU32 maxFreqSupported;
NvU32 ctrl;
NvU32 deviceEntry;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 bufferSize;
NvU32 flags;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 caps;
NvU32 status;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 transmitControl;
NvU32 packetSize;
NvU32 targetHead;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 addr;
NvU32 size;
NvU32 replyType;
NvU32 retryTimeMs;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 data;
NvU32 err;
NvU32 retryTimeMs;
NvU32 eightLaneDpcdBaseAddr;
NvU32 subDeviceInstance;
NvU32 flags;
NvU32 numHeads;
NvU32 subDeviceInstance;
NvU32 headMask;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 numLanes;
NvU32 data[NV0073_CTRL_MAX_LANES];
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 preferredDisplayId;
NvU32 displayIdAssigned;
NvU32 allDisplayMask;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 subDeviceInstance;
NvU32 head;
NvU32 sorIndex;
NvU32 dpLink;
NvU32 displayMask;
NvU32 singleHeadMultistreamMode;
NvU32 hBlankSym;
NvU32 vBlankSym;
NvU32 colorFormat;
NvU32 slotStart;
NvU32 displayMaskDDC;
NvU32 slotEnd;
NvU32 PBN;
NvU32 Timeslice;
NvU32 singleHeadMSTPipeline;
NvU32 tuSize;
NvU32 waterMark;
NvU32 actualPclkHz; // deprecated -Use MvidWarParams
NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams
NvU32 activeCnt;
NvU32 activeFrac;
NvU32 activePolarity;
NvU32 actualPclkHz;
NvU32 linkClkFreqHz;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 mute;
NvU32 addressSpace;
NvU32 cacheSnoop;
NvU32 hclass;
NvU32 channelInstance;
NvU32 subDeviceInstance;
NvU32 offset; // Initial offset for put/get, usually zero.
NvU32 flags;
NvU32 displayId;
NvU32 flags;
NvU32 DDCPartners;
NvU32 count;
NvU32 index;
NvU32 type;
NvU32 location;
NvU32 platform;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 index;
NvU32 type;
NvU32 protocol;
NvU32 ditherType;
NvU32 ditherAlgo;
NvU32 location;
NvU32 rootPortId;
NvU32 dcbIndex;
NvU32 event;
NvU32 action;
NvU32 info32;
NvU32 notifyIndex;
NvU32 data;
NvU32 status;
NvU32 eventDataSize;
NvU32 idr:2;
NvU32 reserved1:14;
NvU32 length:16;
NvU32 hClass;
NvU32 flags;
NvU32 pteAdjust;
NvU32 format;
NvU32 pageCount;
NvU32 fbsrType;
NvU32 numRegions;
NvU32 fbsrType;
NvU32 size;
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
NvU32 numConstructedFalcons;
NvU32 addressSpace;
NvU32 cacheAttrib;
NvU32 gpFifoEntries; // number of GP FIFO entries
NvU32 flags;
NvU32 engineType;
NvU32 cid;
NvU32 subDeviceId;
NvU32 internalFlags; // reserved
NvU32 ProcessID; // reserved
NvU32 SubProcessID; // reserved
NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved
NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
NvU32 numPbdmas;
NvU32 baseIndex;
NvU32 numEntries;
NvU32 engineType;
NvU32 physAttr;
NvU32 engineType;
NvU32 ChID;
NvU32 entryCount;
NvU32 nv2080EngineType;
NvU32 chid;
NvU32 exceptType;
NvU32 scope;
NvU32 size;
NvU32 alignment;
NvU32 version;
NvU32 regBankCount;
NvU32 regBankRegCount;
NvU32 maxWarpsPerSM;
NvU32 maxThreadsPerWarp;
NvU32 geomGsObufEntries;
NvU32 geomXbufEntries;
NvU32 maxSPPerSM;
NvU32 rtCoreCount;
NvU32 numHeads;
NvU32 maxNumHeads;
NvU32 headIndex;
NvU32 maxHResolution;
NvU32 maxVResolution;
NvU32 sriovMaxGfid;
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
NvU32 fbio_mask;
NvU32 fb_bus_width;
NvU32 fb_ram_type;
NvU32 fbp_mask;
NvU32 l2_cache_size;
NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
NvU32 vbiosSubVendor;
NvU32 vbiosSubDevice;
NvU32 performance;
NvU32 newLevel;
NvU32 nameOffset;
NvU32 data;
NvU32 length;
NvU32 size;
NvU32 numEntries;
NvU32 acpiIdListLen;
NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
NvU32 jtCaps;
NvU32 acpiId;
NvU32 mode;
NvU32 tableLen;
NvU32 optimusCaps;
NvU32 numFBRegions;
NvU32 totalVFs;
NvU32 firstVFOffset;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU32 Chipset;
NvU32 hypervisorType;
NvU32 exceptType;
NvU32 runlistId;
NvU32 chid;
NvU32 bufferSizeDWord;
NvU32 cmdIndex;
NvU32 regSaveArea[8];
NvU32 commandBuffer[];
NvU32 addr;
NvU32 val;
NvU32 addr;
NvU32 index;
NvU32 mask;
NvU32 val;
NvU32 addr;
NvU32 mask;
NvU32 val;
NvU32 timeout;
NvU32 flags;
NvU32 error;
NvU32 val;
NvU32 length;
NvU32 addr;
NvU32 index;
NvU32 gpcMask;
NvU32 gspFwHeapFreeListWprOffset;
NvU32 unused0;
NvU32 gpcId;
NvU32 tpcMask;
NvU32 elfCodeOffset;
NvU32 elfDataOffset;
NvU32 elfCodeSize;
NvU32 elfDataSize;
NvU32 lsUcodeVersion;
NvU32 partitionRpcPadding[4];
NvU32 sizeOfCrashReportQueue;
NvU32 gpcId;
NvU32 lsUcodeVersionPadding[1];
NvU32 zcullMask;
NvU32 version; // queue version
NvU32 size; // bytes, page aligned
NvU32 msgSize; // entry size, bytes, must be power-of-2, 16 is minimum
NvU32 msgCount; // number of entries in queue
NvU32 writePtr; // message id of next slot
NvU32 flags; // if set it means "i want to swap RX"
NvU32 rxHdrOff; // Offset of msgqRxHeader from start of backing store.
NvU32 entryOff; // Offset of entries from start of backing store.
NvU32 readPtr; // message id of last message read
NvU32 pageTableEntryCount;
NvU32 oldLevel;
NvU32 flags;
NvU32 BoardID;
NvU32 gpuInstance;
NvU32 businessCycle;
NvU32 padding[24];
((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_POLL) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_DELAY_US) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_STORE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE) / sizeof(NvU32)) : \
NvU32 version; // structure version
NvU32 bootloaderOffset;
NvU32 bootloaderSize;
NvU32 bootloaderParamOffset;
NvU32 bootloaderParamSize;
NvU32 riscvElfOffset;
NvU32 riscvElfSize;
NvU32 appVersion; // Changelist number associated with the image
NvU32 manifestOffset;
NvU32 manifestSize;
NvU32 monitorDataOffset;
NvU32 monitorDataSize;
NvU32 monitorCodeOffset;
NvU32 monitorCodeSize;
NvU32 bIsMonitorEnabled;
NvU32 swbromCodeOffset;
NvU32 swbromCodeSize;
NvU32 swbromDataOffset;
NvU32 swbromDataSize;
NvU32 fbReservedSize;
NvU32 bSignedAsCode;
NvU32 pmcIntrMask;
NvU32 vectorStall;
NvU32 vectorNonStall;
NvU32 tableLen;
NvU32 totalVFs;
NvU32 spare;
NvU32 cpuRmGfid;
NvU32 firstVfOffset;
NvU32 header_version;
NvU32 signature;
NvU32 length;
NvU32 function;
NvU32 rpc_result;
NvU32 vfFeatureMask;
NvU32 rpc_result_private;
NvU32 sequence;
NvU32 checkSum; // Set to value needed to make checksum always zero.
NvU32 seqNum; // Sequence number maintained by the message queue.
NvU32 elemCount; // Number of message queue elements this message has.
NvU32 size;
NvU32 prohibitMultipleInstances;
NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC?
NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG?
NvU32 engineInstance;
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA?
NvU32 numEntries;
NvU32 flags;
NvU32 chId;
NvU32 subDeviceId; // ID+1, 0 for BC
NvU32 pasid;
NvU32 subDeviceId; // ID+1, 0 for BC
NvU32 index;
NvU32 bigPageSize;
NvU32 subDeviceId;
NvU32 numLevelsToCopy;
NvU32 aperture;
NvU32 processID;
NvU32 subDeviceInstance;
NvU32 flags;
NvU32 displayMask;
NvU32 retryTimeMs;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 feHwSysCap;
NvU32 UHBRSupportedByDfp;
NvU32 windowPresentMask;
NvU32 numHeads;
NvU32 i2cPort;
NvU32 internalDispActiveMask;
NvU32 embeddedDisplayPortMask;
NvU32 subDeviceInstance;
NvU32 head;
NvU32 flags;
NvU32 displayId;
NvU32 numDispChannels;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 brightness;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 data;
NvU32 err;
NvU32 retryTimeMs;
NvU32 eightLaneDpcdBaseAddr;
NvU32 subDeviceInstance;
NvU32 head;
NvU32 sorIndex;
NvU32 dpLink;
NvU32 singleHeadMultistreamMode;
NvU32 hBlankSym;
NvU32 vBlankSym;
NvU32 subDeviceInstance;
NvU32 colorFormat;
NvU32 slotStart;
NvU32 slotEnd;
NvU32 PBN;
NvU32 Timeslice;
NvU32 singleHeadMSTPipeline;
NvU32 displayMask;
NvU32 tuSize;
NvU32 waterMark;
NvU32 displayMaskDDC;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 mute;
NvU32 addressSpace;
NvU32 cacheSnoop;
NvU32 hclass;
NvU32 channelInstance;
NvU32 pbTargetAperture;
NvU32 channelPBSize;
NvU32 subDeviceId;
NvU32 offset; // Initial offset for put/get, usually zero.
NvU32 flags;
NvU32 subDeviceId; // One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel in the pushbuffer stream (via SSDM method)
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 DDCPartners;
NvU32 count;
NvU32 index;
NvU32 type;
NvU32 location;
NvU32 platform;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupportedByGpu;
NvU32 minPClkForCompressed;
NvU32 addressSpace;
NvU32 cacheAttrib;
NvU32 nv2080EngineType;
NvU32 chid;
NvU32 gfid;
NvU32 exceptLevel;
NvU32 exceptType;
NvU32 scope;
NvU32 mmuFaultAddrLo;
NvU32 mmuFaultAddrHi;
NvU32 mmuFaultType;
NvU32 rcJournalBufferSize;
NvU32 engDesc;
NvU32 ctxAttr;
NvU32 ctxBufferSize;
NvU32 addrSpaceList;
NvU32 registerBase;
NvU32 numConstructedFalcons;
NvU32 gpFifoEntries; // number of GP FIFO entries
NvU32 flags;
NvU32 engineType;
NvU32 cid;
NvU32 subDeviceId;
NvU32 internalFlags; // reserved
NvU32 ProcessID; // reserved
NvU32 SubProcessID; // reserved
NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved
NvU32 tpcConfigID; // TPC Configuration Id as supported by DTD-PG Feature
NvU32 size;
NvU32 alignment;
NvU32 gpcMask;
NvU32 gpcId;
NvU32 tpcMask;
NvU32 ecidLow;
NvU32 ecidHigh;
NvU32 ecidExtended;
NvU32 sriovMaxGfid;
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
NvU32 fb_bus_width;
NvU32 fb_ram_type;
NvU32 l2_cache_size;
NvU32 vbiosSubVendor;
NvU32 vbiosSubDevice;
NvU32 performance;
NvU32 acpiIdListLen;
NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
NvU32 jtCaps;
NvU32 acpiId;
NvU32 mode;
NvU32 tableLen;
NvU32 optimusCaps;
NvU32 totalVFs;
NvU32 firstVFOffset;
NvU32 linkCap;
NvU32 numFBRegions;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU32 PCIDeviceID;
NvU32 PCISubDeviceID;
NvU32 PCIRevisionID;
NvU32 pcieAtomicsCplDeviceCapMask;
NvU32 Chipset;
NvU32 chipsetL1ssEnable;
NvU32 hypervisorType;
NvU32 gridBuildCsp;
NvU32 exceptType;
NvU32 runlistId;
NvU32 chid;
NvU32 preemptiveRemovalPreviousXid;
NvU32 index;
NvU32 gspFwHeapFreeListWprOffset;
NvU32 unused0;
NvU32 flags;
NvU32 length;
NvU32 elfCodeOffset;
NvU32 elfDataOffset;
NvU32 elfCodeSize;
NvU32 elfDataSize;
NvU32 BoardID;
NvU32 lsUcodeVersion;
NvU32 partitionRpcPadding[4];
NvU32 sizeOfCrashReportQueue;
NvU32 lsUcodeVersionPadding[1];
NvU32 skuConfigVersion;
NvU32 pmuReservedSize;
NvU32 pageTableEntryCount;
NvU32 oldLevel;
NvU32 flags;
NvU32 gpuInstance;
NvU32 businessCycle;
NvU32 internal[32];
NvU32 flags;
NvU32 subrevision;
NvU32 padding[22];
NvU32 regkeys;
NvU32 totalVFs;
NvU32 gspRmDescSize;
NvU32 firstVfOffset;
NvU32 wprCarveoutSize;
NvU32 vfFeatureMask;
NvU32 payloadBufferSize;
NvU32 numHeads;
NvU32 maxNumHeads;
NvU32 headIndex;
NvU32 maxHResolution;
NvU32 maxVResolution;
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA?
NvU32 engineInstance;