drivers/gpu/drm/nouveau/dispnv04/crtc.c

226

seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

227

NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

335

regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

337

regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;

drivers/gpu/drm/nouveau/dispnv04/dac.c

157

saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);

drivers/gpu/drm/nouveau/dispnv04/dac.c

158

NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);

drivers/gpu/drm/nouveau/dispnv04/dac.c

224

NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);

drivers/gpu/drm/nouveau/dispnv04/hw.c

117

seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);

drivers/gpu/drm/nouveau/dispnv04/hw.c

121

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.c

123

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.h

245

uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);

drivers/gpu/drm/nouveau/dispnv04/hw.h

249

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.h

252

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */