drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

463

NUM_LANES, &state->lane_count);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

73

NUM_LANES, num_lanes == LANE_COUNT_ONE ? 0 : num_lanes == LANE_COUNT_TWO ? 1 : 3);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

116

SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

145

type NUM_LANES;\

drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h

37

SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\

drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c

38

NUM_LANES, &state->lane_count);

drivers/phy/xilinx/phy-zynqmp.c

236

struct xpsgtr_phy phys[NUM_LANES];

drivers/phy/xilinx/phy-zynqmp.c

237

struct clk *clk[NUM_LANES];

drivers/phy/xilinx/phy-zynqmp.c

364

for (i = 0; i < NUM_LANES; i++) {

drivers/phy/xilinx/phy-zynqmp.c

836

static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {