ATL2_WRITE_REG
ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
ATL2_WRITE_REG(hw, REG_ISR, 0);
ATL2_WRITE_REG(hw, REG_IMR, 0);
ATL2_WRITE_REG(hw, REG_ISR, 0);
ATL2_WRITE_REG(hw, REG_IMR, 0);
ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN +