NUM_CHANNELS
u64 dimm_s_size[NUM_CHANNELS];
u64 dimm_l_size[NUM_CHANNELS];
int dimm_l_map[NUM_CHANNELS];
for (i = 0; i < NUM_CHANNELS; i++) {
for (i = 0; i < NUM_CHANNELS; i++) {
u32 reg_mad_inter_size_mask[NUM_CHANNELS];
layers[0].size = NUM_CHANNELS;
: NUM_CHANNELS;
for (i = 0; i < NUM_CHANNELS; i++) {
for (i = 0; i < NUM_CHANNELS; i++) {
if (channel >= NUM_CHANNELS) {
first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
KNL_MAX_CHANNELS : NUM_CHANNELS;
struct pci_dev *pci_tad[NUM_CHANNELS];
struct sbridge_channel channel[NUM_CHANNELS];
} chan[NUM_CHANNELS];
i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++)
.nr = NUM_CHANNELS,
for (i = 0; i < NUM_CHANNELS; i++)
for (i = 0; i < NUM_CHANNELS; i++) {
static struct uart_ip22zilog_port ip22zilog_port_table[NUM_CHANNELS];
#define BYTES_PER_FRAME (NUM_CHANNELS * BYTES_PER_SAMPLE)
(f * NUM_CHANNELS);
for (c = 0; c < NUM_CHANNELS; c++) {
.channels_min = NUM_CHANNELS,
.channels_max = NUM_CHANNELS,