drivers/gpu/drm/nouveau/dispnv04/crtc.c

196

NV_CIO_CRE_RPC1_INDEX) & ~0xC0;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

233

NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

392

regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?

drivers/gpu/drm/nouveau/dispnv04/dac.c

169

saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);

drivers/gpu/drm/nouveau/dispnv04/dac.c

170

NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);

drivers/gpu/drm/nouveau/dispnv04/dac.c

223

NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);

drivers/gpu/drm/nouveau/dispnv04/dac.c

285

if (!(NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX) & 0xC0))

drivers/gpu/drm/nouveau/dispnv04/hw.c

599

rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);

drivers/gpu/drm/nouveau/dispnv04/hw.c

713

wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

89

crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

97

NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);