drivers/gpu/drm/nouveau/dispnv04/crtc.c

227

NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);

drivers/gpu/drm/nouveau/dispnv04/dac.c

158

NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);

drivers/gpu/drm/nouveau/dispnv04/dac.c

224

NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);

drivers/gpu/drm/nouveau/dispnv04/hw.c

121

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.c

123

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.c

295

NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);

drivers/gpu/drm/nouveau/dispnv04/hw.c

351

NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);

drivers/gpu/drm/nouveau/dispnv04/hw.c

364

NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);

drivers/gpu/drm/nouveau/dispnv04/hw.c

365

NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);

drivers/gpu/drm/nouveau/dispnv04/hw.c

573

NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);

drivers/gpu/drm/nouveau/dispnv04/hw.h

240

NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);

drivers/gpu/drm/nouveau/dispnv04/hw.h

249

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);

drivers/gpu/drm/nouveau/dispnv04/hw.h

252

NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */

drivers/gpu/drm/nouveau/dispnv04/hw.h

37

void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);