drivers/gpu/drm/nouveau/dispnv50/base507c.c

110

NVDEF(NV507C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

drivers/gpu/drm/nouveau/dispnv50/base507c.c

111

NVDEF(NV507C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

drivers/gpu/drm/nouveau/dispnv50/base507c.c

112

NVDEF(NV507C, SURFACE_SET_PARAMS, LAYOUT, FRM) |

drivers/gpu/drm/nouveau/dispnv50/base507c.c

114

NVDEF(NV507C, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

128

NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

142

NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, USE_CORE_LUT));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

192

NVDEF(NV_DISP_BASE_NOTIFIER_1, _0, STATUS, NOT_BEGUN));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

58

NVDEF(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING) |

drivers/gpu/drm/nouveau/dispnv50/base507c.c

82

NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),

drivers/gpu/drm/nouveau/dispnv50/base507c.c

89

NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE),

drivers/gpu/drm/nouveau/dispnv50/base827c.c

45

NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),

drivers/gpu/drm/nouveau/dispnv50/base827c.c

52

NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE),

drivers/gpu/drm/nouveau/dispnv50/base827c.c

74

NVDEF(NV827C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

drivers/gpu/drm/nouveau/dispnv50/base827c.c

75

NVDEF(NV827C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

drivers/gpu/drm/nouveau/dispnv50/base827c.c

76

NVDEF(NV827C, SURFACE_SET_PARAMS, LAYOUT, FRM));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

100

NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

166

NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

180

NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) |

drivers/gpu/drm/nouveau/dispnv50/base907c.c

39

NVDEF(NV907C, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/base907c.c

59

NVDEF(NV907C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

drivers/gpu/drm/nouveau/dispnv50/base907c.c

60

NVDEF(NV907C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

drivers/gpu/drm/nouveau/dispnv50/base907c.c

61

NVDEF(NV907C, SURFACE_SET_PARAMS, LAYOUT, FRM));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

75

NVDEF(NV907C, SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

78

NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

112

NVDEF(NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, FALSE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

44

NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

46

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

51

NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

52

NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

53

NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE),

drivers/gpu/drm/nouveau/dispnv50/core507d.c

56

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

77

NVDEF(NV_DISP_CORE_NOTIFIER_1, COMPLETION_0, DONE, FALSE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

91

NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

93

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

98

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/core907d.c

41

NVDEF(NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, FALSE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

141

NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

142

NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

143

NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

144

NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

145

NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, YUV_PACKED422, TRUE),

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

151

NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_LUT, USAGE_1025) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

152

NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

153

NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

45

NVDEF(NVC37D, WINDOW_SET_CONTROL, OWNER, HEAD(i >> 1)));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

62

NVDEF(NVC37D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

64

NVDEF(NVC37D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

70

NVDEF(NVC37D, UPDATE, SPECIAL_HANDLING, NONE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

71

NVDEF(NVC37D, UPDATE, INHIBIT_INTERRUPTS, FALSE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

75

NVDEF(NVC37D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

97

NVDEF(NV_DISP_NOTIFIER, _0, STATUS, NOT_BEGUN));

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

44

NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

45

NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

46

NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

47

NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE),

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

53

NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, ILUT_ALLOWED, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

54

NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) |

drivers/gpu/drm/nouveau/dispnv50/corec57d.c

55

NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

33

NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

34

NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

37

NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, MODE, WRITE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

38

NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

45

NVDEF(NVCA7D, UPDATE, RELEASE_ELV, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

46

NVDEF(NVCA7D, UPDATE, SPECIAL_HANDLING, NONE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

47

NVDEF(NVCA7D, UPDATE, INHIBIT_INTERRUPTS, FALSE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

51

NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

70

NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

71

NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

72

NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

73

NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE),

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

79

NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, ILUT_ALLOWED, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

80

NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

81

NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE),

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

88

NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

89

NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, OLUT_ALLOWED, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

90

NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_SCALER_TAPS, TAPS_2) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

91

NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

31

u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

32

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

33

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

34

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE) |

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

35

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

36

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, WIDE_PIPE_CRC, ENABLE);

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

41

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SOR(or));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

44

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, PIOR(or));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

47

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, DAC(or));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

50

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, RG(i));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

53

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

56

crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE);

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

21

NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

22

NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

23

NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE);

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

28

crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or));

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

31

crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, PIOR(or));

drivers/gpu/drm/nouveau/dispnv50/crcc37d.c

34

crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

18

u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

19

NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

20

NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

21

NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE);

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

26

crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or));

drivers/gpu/drm/nouveau/dispnv50/crcc57d.c

29

crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

32

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

33

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

36

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

80

NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

81

NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

83

NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

84

NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/curs507a.c

53

NVDEF(NV507A, UPDATE, INTERLOCK_WITH_CORE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/disp.c

1974

const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1991

case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

1992

case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

2010

ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);

drivers/gpu/drm/nouveau/dispnv50/disp.c

2013

ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);

drivers/gpu/drm/nouveau/dispnv50/disp.c

486

const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);

drivers/gpu/drm/nouveau/dispnv50/disp.c

503

case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

504

case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

505

case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

506

case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

512

ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);

drivers/gpu/drm/nouveau/dispnv50/head507d.c

104

case 8: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

105

case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

106

case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

107

case 1: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

112

bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);

drivers/gpu/drm/nouveau/dispnv50/head507d.c

133

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

134

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

135

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));

drivers/gpu/drm/nouveau/dispnv50/head507d.c

150

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

155

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

156

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),

drivers/gpu/drm/nouveau/dispnv50/head507d.c

228

NVDEF(NV507D, HEAD_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256),

drivers/gpu/drm/nouveau/dispnv50/head507d.c

289

NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head507d.c

304

NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

358

NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

359

NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, ADJ1000DIV1001, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

360

NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, NOT_DRIVER, FALSE),

drivers/gpu/drm/nouveau/dispnv50/head507d.c

40

NVDEF(NV507D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

41

NVDEF(NV507D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

411

NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

412

NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

44

NVDEF(NV507D, HEAD_SET_PROCAMP, TRANSITION, HARD));

drivers/gpu/drm/nouveau/dispnv50/head507d.c

76

case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

77

case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;

drivers/gpu/drm/nouveau/dispnv50/head507d.c

82

bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);

drivers/gpu/drm/nouveau/dispnv50/head507d.c

84

bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16);

drivers/gpu/drm/nouveau/dispnv50/head827d.c

121

NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head827d.c

138

NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

40

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

41

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

42

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));

drivers/gpu/drm/nouveau/dispnv50/head827d.c

59

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

64

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

65

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),

drivers/gpu/drm/nouveau/dispnv50/head827d.c

98

NVDEF(NV827D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

99

NVDEF(NV827D, HEAD_SET_PARAMS, GAMMA, LINEAR),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

105

case 8: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

106

case 4: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

107

case 2: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

112

bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, USABLE, TRUE);

drivers/gpu/drm/nouveau/dispnv50/head907d.c

114

bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16);

drivers/gpu/drm/nouveau/dispnv50/head907d.c

134

case 8: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

135

case 4: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

136

case 2: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

137

case 1: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;

drivers/gpu/drm/nouveau/dispnv50/head907d.c

142

bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);

drivers/gpu/drm/nouveau/dispnv50/head907d.c

163

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

164

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

165

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));

drivers/gpu/drm/nouveau/dispnv50/head907d.c

182

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

187

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

234

NVDEF(NV907D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

235

NVDEF(NV907D, HEAD_SET_PARAMS, GAMMA, LINEAR),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

257

NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head907d.c

274

NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

276

NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

365

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

368

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

369

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

370

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE),

drivers/gpu/drm/nouveau/dispnv50/head907d.c

374

NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE));

drivers/gpu/drm/nouveau/dispnv50/head907d.c

389

NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

390

NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

68

NVDEF(NV907D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

69

NVDEF(NV907D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

72

NVDEF(NV907D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

73

NVDEF(NV907D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head917d.c

58

case 8: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;

drivers/gpu/drm/nouveau/dispnv50/head917d.c

59

case 4: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;

drivers/gpu/drm/nouveau/dispnv50/head917d.c

60

case 2: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;

drivers/gpu/drm/nouveau/dispnv50/head917d.c

61

case 1: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;

drivers/gpu/drm/nouveau/dispnv50/head917d.c

66

bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);

drivers/gpu/drm/nouveau/dispnv50/head917d.c

67

bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, BASE_LUT, USAGE_1025);

drivers/gpu/drm/nouveau/dispnv50/head917d.c

89

NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head917d.c

94

NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

115

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

116

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

133

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

138

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, DE_GAMMA, NONE),

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

142

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

144

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

146

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

248

NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

249

NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

250

NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

60

NVDEF(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

75

NVDEF(NVC37D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

76

NVDEF(NVC37D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

79

NVDEF(NVC37D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

80

NVDEF(NVC37D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

81

NVDEF(NVC37D, HEAD_SET_PROCAMP, BLACK_LEVEL, GRAPHICS));

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

98

NVDEF(NVC37D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

122

NVDEF(NVC57D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

240

NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

241

NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OLUT_ALLOWED, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

242

NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_SCALER_TAPS, TAPS_2) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

243

NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

73

NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

74

NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE));

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

90

NVDEF(NVC57D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

91

NVDEF(NVC57D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

92

NVDEF(NVC57D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

103

NVDEF(NVCA7D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

122

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

123

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

126

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

148

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

149

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

152

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

160

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

162

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

164

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

181

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

203

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

204

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

208

NVDEF(NVCA7D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

246

NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, PROGRESSIVE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

64

NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

65

NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

82

NVDEF(NVCA7D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

83

NVDEF(NVCA7D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

84

NVDEF(NVCA7D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA));

drivers/gpu/drm/nouveau/dispnv50/ovly507e.c

65

NVDEF(NV507E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |

drivers/gpu/drm/nouveau/dispnv50/ovly507e.c

71

NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));

drivers/gpu/drm/nouveau/dispnv50/ovly507e.c

89

NVDEF(NV507E, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));

drivers/gpu/drm/nouveau/dispnv50/ovly827e.c

42

NVDEF(NV827E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |

drivers/gpu/drm/nouveau/dispnv50/ovly827e.c

48

NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));

drivers/gpu/drm/nouveau/dispnv50/ovly827e.c

87

NVDEF(NV_DISP_NOTIFICATION_1, _3, STATUS, NOT_BEGUN));

drivers/gpu/drm/nouveau/dispnv50/ovly907e.c

39

NVDEF(NV907E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |

drivers/gpu/drm/nouveau/dispnv50/ovly907e.c

45

NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE));

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

105

NVDEF(NVC37E, SET_COMPOSITION_CONTROL, COLOR_KEY_SELECT, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

151

NVDEF(NVC37E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING));

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

169

NVDEF(NVC37E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

182

NVDEF(NVC37E, SET_PARAMS, INPUT_RANGE, BYPASS) |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

183

NVDEF(NVC37E, SET_PARAMS, UNDERREPLICATE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

184

NVDEF(NVC37E, SET_PARAMS, DE_GAMMA, NONE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

186

NVDEF(NVC37E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

187

NVDEF(NVC37E, SET_PARAMS, SWAP_UV, DISABLE),

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c

44

NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c

56

NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c

57

NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c

58

NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c

41

NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c

52

NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c

53

NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c

54

NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

107

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

128

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

129

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

150

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

173

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

174

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

26

NVDEF(NVCA7E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

29

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

55

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, TARGET, PHYSICAL_NVM) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

57

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

62

NVDEF(NVCA7E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

73

NVDEF(NVCA7E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

74

NVDEF(NVCA7E, SET_PARAMS, SWAP_UV, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

75

NVDEF(NVCA7E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),

drivers/gpu/drm/nouveau/gv100_fence.c

30

NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |

drivers/gpu/drm/nouveau/gv100_fence.c

31

NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |

drivers/gpu/drm/nouveau/gv100_fence.c

32

NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |

drivers/gpu/drm/nouveau/gv100_fence.c

33

NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));

drivers/gpu/drm/nouveau/gv100_fence.c

37

MEM_OP_C, NVDEF(NVC36F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR),

drivers/gpu/drm/nouveau/gv100_fence.c

38

MEM_OP_D, NVDEF(NVC36F, MEM_OP_D, OPERATION, MEMBAR));

drivers/gpu/drm/nouveau/gv100_fence.c

61

NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |

drivers/gpu/drm/nouveau/gv100_fence.c

62

NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |

drivers/gpu/drm/nouveau/gv100_fence.c

63

NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));

drivers/gpu/drm/nouveau/include/nvif/push206e.h

9

PUSH_DATA__((p), NVDEF(NV206E, DMA, OPCODE2, CALL) | \

drivers/gpu/drm/nouveau/include/nvif/push507c.h

10

PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, METHOD) | \

drivers/gpu/drm/nouveau/include/nvif/push507c.h

21

PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, JUMP) | \

drivers/gpu/drm/nouveau/include/nvif/push906f.h

30

NVDEF(NV906F, DMA, SEC_OP, o), \

drivers/gpu/drm/nouveau/include/nvif/pushc37b.h

10

PUSH_DATA__((p), NVDEF(NVC37B, DMA, OPCODE, METHOD) | \

drivers/gpu/drm/nouveau/include/nvif/pushc97b.h

10

PUSH_DATA__((p), NVDEF(NVC97B, DMA, OPCODE, METHOD) | \

drivers/gpu/drm/nouveau/nouveau_bo5039.c

103

NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH));

drivers/gpu/drm/nouveau/nouveau_bo5039.c

120

NVDEF(NV5039, FORMAT, IN, ONE) |

drivers/gpu/drm/nouveau/nouveau_bo5039.c

121

NVDEF(NV5039, FORMAT, OUT, ONE),

drivers/gpu/drm/nouveau/nouveau_bo5039.c

124

NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY));

drivers/gpu/drm/nouveau/nouveau_bo5039.c

64

NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR),

drivers/gpu/drm/nouveau/nouveau_bo5039.c

67

NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) |

drivers/gpu/drm/nouveau/nouveau_bo5039.c

68

NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) |

drivers/gpu/drm/nouveau/nouveau_bo5039.c

69

NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB),

drivers/gpu/drm/nouveau/nouveau_bo5039.c

81

NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH));

drivers/gpu/drm/nouveau/nouveau_bo5039.c

86

NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR),

drivers/gpu/drm/nouveau/nouveau_bo5039.c

89

NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) |

drivers/gpu/drm/nouveau/nouveau_bo5039.c

90

NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) |

drivers/gpu/drm/nouveau/nouveau_bo5039.c

91

NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB),

drivers/gpu/drm/nouveau/nouveau_bo9039.c

71

NVDEF(NV9039, LAUNCH_DMA, SRC_INLINE, FALSE) |

drivers/gpu/drm/nouveau/nouveau_bo9039.c

72

NVDEF(NV9039, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_bo9039.c

73

NVDEF(NV9039, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_bo9039.c

74

NVDEF(NV9039, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) |

drivers/gpu/drm/nouveau/nouveau_bo9039.c

75

NVDEF(NV9039, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_bo9039.c

76

NVDEF(NV9039, LAUNCH_DMA, SEMAPHORE_STRUCT_SIZE, ONE_WORD));

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

64

NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

65

NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

66

NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

67

NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

68

NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

69

NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

70

NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

71

NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

72

NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

73

NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, VIRTUAL) |

drivers/gpu/drm/nouveau/nouveau_boa0b5.c

74

NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL));

drivers/gpu/drm/nouveau/nouveau_connector.h

71

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, DISABLE),

drivers/gpu/drm/nouveau/nouveau_connector.h

73

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, ENABLE),

drivers/gpu/drm/nouveau/nouveau_connector.h

75

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, DYNAMIC_2X2),

drivers/gpu/drm/nouveau/nouveau_connector.h

77

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, STATIC_2X2),

drivers/gpu/drm/nouveau/nouveau_connector.h

79

NVDEF(NV907D, HEAD_SET_DITHER_CONTROL, MODE, TEMPORAL),

drivers/gpu/drm/nouveau/nouveau_connector.h

84

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_6_BITS),

drivers/gpu/drm/nouveau/nouveau_connector.h

86

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_8_BITS),

drivers/gpu/drm/nouveau/nouveau_dmem.c

570

NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB));

drivers/gpu/drm/nouveau/nouveau_dmem.c

574

NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM));

drivers/gpu/drm/nouveau/nouveau_dmem.c

580

launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, PHYSICAL);

drivers/gpu/drm/nouveau/nouveau_dmem.c

587

NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));

drivers/gpu/drm/nouveau/nouveau_dmem.c

591

NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));

drivers/gpu/drm/nouveau/nouveau_dmem.c

597

launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);

drivers/gpu/drm/nouveau/nouveau_dmem.c

615

NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

616

NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

617

NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

618

NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

619

NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

620

NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

621

NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

622

NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

623

NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING));

drivers/gpu/drm/nouveau/nouveau_dmem.c

642

NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));

drivers/gpu/drm/nouveau/nouveau_dmem.c

646

NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));

drivers/gpu/drm/nouveau/nouveau_dmem.c

652

launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);

drivers/gpu/drm/nouveau/nouveau_dmem.c

658

NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

659

NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

660

NVDEF(NVA0B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

661

NVDEF(NVA0B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO));

drivers/gpu/drm/nouveau/nouveau_dmem.c

671

NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

672

NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

673

NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

674

NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

675

NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

676

NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

677

NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

678

NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) |

drivers/gpu/drm/nouveau/nouveau_dmem.c

679

NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING));

drivers/gpu/drm/nouveau/nv84_fence.c

50

NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),

drivers/gpu/drm/nouveau/nv84_fence.c

73

NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));

drivers/gpu/drm/nouveau/nvc0_fence.c

47

NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |

drivers/gpu/drm/nouveau/nvc0_fence.c

48

NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) |

drivers/gpu/drm/nouveau/nvc0_fence.c

49

NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE),

drivers/gpu/drm/nouveau/nvc0_fence.c

70

NVDEF(NV906F, SEMAPHORED, OPERATION, ACQ_GEQ) |

drivers/gpu/drm/nouveau/nvc0_fence.c

71

NVDEF(NV906F, SEMAPHORED, ACQUIRE_SWITCH, ENABLED));

drivers/gpu/drm/nouveau/nvif/chan906f.c

39

NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |

drivers/gpu/drm/nouveau/nvif/chan906f.c

40

NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, DIS) |

drivers/gpu/drm/nouveau/nvif/chan906f.c

41

NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE));

drivers/gpu/drm/nouveau/nvif/chanc36f.c

43

NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |

drivers/gpu/drm/nouveau/nvif/chanc36f.c

44

NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, DIS) |

drivers/gpu/drm/nouveau/nvif/chanc36f.c

45

NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |

drivers/gpu/drm/nouveau/nvif/chanc36f.c

46

NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

219

msg.nvdm_header = NVDEF(MCTP, MSG_HEADER, TYPE, VENDOR_PCI) |

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

220

NVDEF(MCTP, MSG_HEADER, VENDOR_ID, NV) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

332

ctrl->ctrl = NVDEF(NV0073, CTRL_DFP_ELD_AUDIO_CAPS_CTRL, PD, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

333

ctrl->ctrl |= NVDEF(NV0073, CTRL_DFP_ELD_AUDIO_CAPS_CTRL, ELDV, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

487

ctrl->caps |= NVDEF(NV0073_CTRL_CMD_SPECIFIC, SET_HDMI_SINK_CAPS, SCDC_SUPPORTED, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

489

ctrl->caps |= NVDEF(NV0073_CTRL_CMD_SPECIFIC, SET_HDMI_SINK_CAPS, GT_340MHZ_CLOCK_SUPPORTED, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

491

ctrl->caps |= NVDEF(NV0073_CTRL_CMD_SPECIFIC, SET_HDMI_SINK_CAPS, LTE_340MHZ_SCRAMBLING_SUPPORTED, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

525

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, ENABLE, YES) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

526

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, OTHER_FRAME, DISABLE) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

527

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, SINGLE_FRAME, DISABLE) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

528

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, ON_HBLANK, DISABLE) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

529

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, VIDEO_FMT, SW_CONTROLLED) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

530

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, RESERVED_LEGACY_MODE, NO);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

706

ctrl->flags |= NVDEF(NV0073_CTRL, DFP_ASSIGN_SOR_FLAGS, AUDIO, OPTIMAL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

972

cmd = NVDEF(NV0073_CTRL, DP_CMD, SET_LANE_COUNT, TRUE) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

973

NVDEF(NV0073_CTRL, DP_CMD, SET_LINK_BW, TRUE) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

974

NVDEF(NV0073_CTRL, DP_CMD, TRAIN_PHY_REPEATER, YES);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

980

cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_FORMAT_MODE, MULTI_STREAM);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

983

cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_ENHANCED_FRAMING, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

988

cmd |= NVDEF(NV0073_CTRL, DP_CMD, POST_LT_ADJ_REQ_GRANTED, YES);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

71

rpc->flags = NVDEF(NVOS02, FLAGS, PHYSICALITY, NONCONTIGUOUS) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

72

NVDEF(NVOS02, FLAGS, LOCATION, PCI) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

73

NVDEF(NVOS02, FLAGS, MAPPING, NO_MAP);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

76

rpc->flags = NVDEF(NVOS02, FLAGS, PHYSICALITY, CONTIGUOUS) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

77

NVDEF(NVOS02, FLAGS, LOCATION, VIDMEM) |

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c

78

NVDEF(NVOS02, FLAGS, MAPPING, NO_MAP);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

101

args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

102

args->flags |= NVDEF(NVOS04, FLAGS, DELAY_CHANNEL_SCHEDULING, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

103

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_PHYSICAL_MODE_CE, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

106

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_FIXED, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

108

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_FIXED, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

110

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_AUTH_LEVEL_PRIV, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

111

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_SCRUBBER, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

112

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_CLIENT_MAP_FIFO, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

113

args->flags |= NVDEF(NVOS04, FLAGS, SET_EVICT_LAST_CE_PREFETCH_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

114

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_VGPU_PLUGIN_CONTEXT, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

115

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_PBDMA_ACQUIRE_TIMEOUT, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

116

args->flags |= NVDEF(NVOS04, FLAGS, GROUP_CHANNEL_THREAD, DEFAULT);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

117

args->flags |= NVDEF(NVOS04, FLAGS, MAP_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

118

args->flags |= NVDEF(NVOS04, FLAGS, SKIP_CTXBUFFER_ALLOC, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

144

args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, USER);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

146

args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, ADMIN);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

147

args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ERROR_NOTIFIER_TYPE, NONE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

148

args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ECC_ERROR_NOTIFIER_TYPE, NONE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

94

args->flags = NVDEF(NVOS04, FLAGS, CHANNEL_TYPE, PHYSICAL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

95

args->flags |= NVDEF(NVOS04, FLAGS, VPR, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

96

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_MAP_REFCOUNTING, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

99

args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c

143

ctrl->flags = NVDEF(NV0080_CTRL_DMA_SET_PAGE_DIRECTORY, FLAGS, APERTURE, VIDMEM);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

39

args->flags = NVDEF(NVOS04, FLAGS, CHANNEL_TYPE, PHYSICAL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

40

args->flags |= NVDEF(NVOS04, FLAGS, VPR, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

41

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_MAP_REFCOUNTING, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

44

args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

46

args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

47

args->flags |= NVDEF(NVOS04, FLAGS, DELAY_CHANNEL_SCHEDULING, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

48

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_PHYSICAL_MODE_CE, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

51

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_FIXED, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

53

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_FIXED, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

55

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_AUTH_LEVEL_PRIV, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

56

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_SCRUBBER, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

57

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_CLIENT_MAP_FIFO, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

58

args->flags |= NVDEF(NVOS04, FLAGS, SET_EVICT_LAST_CE_PREFETCH_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

59

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_VGPU_PLUGIN_CONTEXT, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

60

args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_PBDMA_ACQUIRE_TIMEOUT, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

61

args->flags |= NVDEF(NVOS04, FLAGS, GROUP_CHANNEL_THREAD, DEFAULT);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

62

args->flags |= NVDEF(NVOS04, FLAGS, MAP_CHANNEL, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

63

args->flags |= NVDEF(NVOS04, FLAGS, SKIP_CTXBUFFER_ALLOC, FALSE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

89

args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, USER);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

91

args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, ADMIN);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

92

args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ERROR_NOTIFIER_TYPE, NONE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c

93

args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ECC_ERROR_NOTIFIER_TYPE, NONE);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

117

*data |= NVDEF(NV_MMU, VER3_PDE, APERTURE, VIDEO_MEMORY);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

118

*data |= NVDEF(NV_MMU, VER3_PDE, PCF, VALID_CACHED_ATS_NOT_ALLOWED);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

121

*data |= NVDEF(NV_MMU, VER3_PDE, APERTURE, SYSTEM_COHERENT_MEMORY);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

122

*data |= NVDEF(NV_MMU, VER3_PDE, PCF, VALID_UNCACHED_ATS_ALLOWED);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

125

*data |= NVDEF(NV_MMU, VER3_PDE, APERTURE, SYSTEM_NON_COHERENT_MEMORY);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

126

*data |= NVDEF(NV_MMU, VER3_PDE, PCF, VALID_CACHED_ATS_ALLOWED);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

158

const u64 data = NVDEF(NV_MMU, VER3_DUAL_PDE, PCF_BIG, SPARSE_ATS_ALLOWED);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

272

map->type |= NVDEF(NV_MMU, VER3_PTE, VALID, TRUE);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

62

const u64 data = NVDEF(NV_MMU, VER3_PTE, PCF, SPARSE);

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgh100.c

80

const u64 data = NVDEF(NV_MMU, VER3_PTE, PCF, NO_VALID_4KB_PAGE);