NUM_OF_EDMA_PER_DCORE
for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
static const u32 gaudi2_edma_initiator_hbw_sft[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
hw_test_cap_bit = HW_CAP_EDMA_SHIFT + NUM_OF_EDMA_PER_DCORE +
hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 2 * NUM_OF_EDMA_PER_DCORE +
hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 3 * NUM_OF_EDMA_PER_DCORE +
for (j = 0 ; j < NUM_OF_EDMA_PER_DCORE ; j++) {
int seq = i * NUM_OF_EDMA_PER_DCORE + j;
edma_seq_base = dcore_id * NUM_OF_EDMA_PER_DCORE;
return (((module_idx / NUM_OF_EDMA_PER_DCORE) * ENGINE_ID_DCORE_OFFSET) +
(module_idx % NUM_OF_EDMA_PER_DCORE));
dcore_id = module_idx / NUM_OF_EDMA_PER_DCORE;
for (mod_idx = 0 ; mod_idx < (NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)
extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];