NUM_OF_DCORES
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
u32 i, mmu_id, num_of_hmmus = NUM_OF_HMMU_PER_DCORE * NUM_OF_DCORES;
const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
static const u32 gaudi2_tpc_initiator_hbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
static const u32 gaudi2_tpc_initiator_lbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
static const u32 gaudi2_edma_initiator_hbw_sft[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
gaudi2_mme_initiator_rtr_id[NUM_OF_MME_PER_DCORE * NUM_OF_DCORES] = {
for (dcore = 0; dcore < NUM_OF_DCORES; dcore++) {
for (i = 1; i < NUM_OF_DCORES; ++i) {
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++) {
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++)
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++)
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++) {
enum gaudi2_queue_id dcore_tpc_qid_base[NUM_OF_DCORES];
seq = NUM_OF_DCORES * NUM_OF_TPC_PER_DCORE;
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
for (i = 0; i < NUM_OF_DCORES; i++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++) {
for (i = 0 ; i < NUM_OF_DCORES ; i++) {
if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 0))
if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 1))
for (i = 0 ; i < NUM_OF_DCORES ; i++)
if (module_idx == (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES))
for (mod_idx = 0 ; mod_idx < (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1) ; mod_idx++) {
for (mod_idx = 0 ; mod_idx < (NUM_OF_MME_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)
for (mod_idx = 0 ; mod_idx < (NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)
if (dec_index < NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES)
(dec_index - NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES);
#define NUMBER_OF_DEC ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC)
#define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];
for (i = 1 ; i < NUM_OF_DCORES ; i++) {
block_ctx.blocks = NUM_OF_DCORES;
block_ctx.blocks = NUM_OF_DCORES;
for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,