drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

159

#ifndef NUMBER_OF_M3ARB_PARAM_SETS

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

171

uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */

drivers/gpu/drm/radeon/sumo_dpm.c

1691

for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {

drivers/gpu/drm/radeon/sumo_dpm.h

91

u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];

drivers/gpu/drm/radeon/sumo_dpm.h

92

u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];

drivers/gpu/drm/radeon/sumo_dpm.h

93

u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];

drivers/gpu/drm/radeon/sumo_smc.c

77

for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)

drivers/gpu/drm/radeon/sumo_smc.c

81

for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)

drivers/gpu/drm/radeon/sumo_smc.c

83

pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);

drivers/gpu/drm/radeon/sumo_smc.c

85

for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)

drivers/gpu/drm/radeon/sumo_smc.c

87

pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);