arch/mips/ath25/ar2315.c

211

refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);

arch/mips/ath25/ar2315.c

213

fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);

arch/mips/ath25/ar2315.c

214

divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;

arch/mips/ath25/ar2315.c

221

clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);

arch/mips/ath25/ar2315.c

225

clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);

arch/mips/ath25/ar2315.c

234

cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);

arch/mips/ath25/ar2315.c

266

memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);

arch/mips/ath25/ar2315.c

267

memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);

arch/mips/ath25/ar2315.c

268

memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);

arch/mips/ath25/ar5312.c

361

bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);

arch/mips/ath25/ar5312.c

362

bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);