NCR5380_read
if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE)) {
if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) ||
(NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) ||
(NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) {
if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE))
if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {
if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) {
*d = NCR5380_read(CURRENT_SCSI_DATA_REG);
tmp = NCR5380_read(STATUS_REG);
PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
(void)NCR5380_read(RESET_PARITY_INTERRUPT_REG);
tmp = NCR5380_read(STATUS_REG) & PHASE_MASK;
if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {
(NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
(NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
d[c] = NCR5380_read(INPUT_DATA_REG);
} else if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH) {
tmp = NCR5380_read(STATUS_REG);
while (NCR5380_read(STATUS_REG) & SR_REQ)
!(NCR5380_read(STATUS_REG) & SR_BSY)) {
target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask);
if ((NCR5380_read(STATUS_REG) & (SR_BSY | SR_SEL)) == 0)
msg[0] = NCR5380_read(CURRENT_SCSI_DATA_REG);
if ((NCR5380_read(reg1) & bit1) == val1)
if ((NCR5380_read(reg2) & bit2) == val2)
if ((NCR5380_read(reg1) & bit1) == val1)
if ((NCR5380_read(reg2) & bit2) == val2)
status = NCR5380_read(STATUS_REG);
mr = NCR5380_read(MODE_REG);
icr = NCR5380_read(INITIATOR_COMMAND_REG);
basr = NCR5380_read(BUS_AND_STATUS_REG);
status = NCR5380_read(STATUS_REG);
NCR5380_read(STATUS_REG);
for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {
if ((NCR5380_read(BUS_AND_STATUS_REG) &
saved_data = NCR5380_read(INPUT_DATA_REG);
if ((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) ==
NCR5380_read(BUS_AND_STATUS_REG));
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {
basr = NCR5380_read(BUS_AND_STATUS_REG);
unsigned char mr = NCR5380_read(MODE_REG);
unsigned char sr = NCR5380_read(STATUS_REG);
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
} else if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
if ((NCR5380_read(reg) & bit) == val)
PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
NCR5380_read(RESET_PARITY_INTERRUPT_REG);
if (NCR5380_read(MODE_REG) != 0) {
if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)
NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY)
NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) {
if (start >= len && NCR5380_read(hostdata->c400_blk_cnt) == 0)
if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) {
basr = NCR5380_read(BUS_AND_STATUS_REG);