NAU8821_R01_ENA_CTRL
{ NAU8821_R01_ENA_CTRL, 0x00ff },
case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,