drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

42

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

39

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

49

adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

494

.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

495

.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

496

.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

142

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

170

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

287

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

134

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

165

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

169

.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

172

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

168

.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

176

.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

193

.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

210

.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

196

.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

207

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

211

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

187

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

191

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

192

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

196

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

178

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

181

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/include/aldebaran_ip_offset.h

147

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },

drivers/gpu/drm/amd/include/beige_goby_ip_offset.h

136

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },

drivers/gpu/drm/amd/include/cyan_skillfish_ip_offset.h

97

static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },

drivers/gpu/drm/amd/include/dimgrey_cavefish_ip_offset.h

121

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },

drivers/gpu/drm/amd/include/navi10_ip_offset.h

97

static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },

drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h

128

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },

drivers/gpu/drm/amd/include/vangogh_ip_offset.h

160

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },

drivers/gpu/drm/amd/include/vega10_ip_offset.h

41

static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },

drivers/gpu/drm/amd/include/vega20_ip_offset.h

97

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },

drivers/gpu/drm/amd/include/yellow_carp_offset.h

131

static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },