NBIO_HWIP
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
[NBIO_HWIP] = "NBIO",
[NBIO_HWIP] = NBIF_HWID,
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) != IP_VERSION(3, 3, 0))
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) &&
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4))
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
init_config.nbio_ip_version = amdgpu_ip_version(adev, NBIO_HWIP, 0);