NAU8825_REG_ENA_CTRL
SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
{ NAU8825_REG_ENA_CTRL, 0x00ff },
regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);