MXL862XX_API_WRITE
MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_DISABLE, dis);
MXL862XX_API_WRITE(priv, MXL862XX_XPCS_AN_RESTART, an);
MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_LINK_UP, lu);
ret = MXL862XX_API_WRITE(priv, MXL862XX_MAC_TABLEENTRYADD, param);
ret = MXL862XX_API_WRITE(priv, MXL862XX_MAC_TABLEENTRYREMOVE, param);
return MXL862XX_API_WRITE(priv, MXL862XX_MAC_TABLEENTRYADD, aparam);
ret = MXL862XX_API_WRITE(priv, MXL862XX_MAC_TABLEENTRYREMOVE, rparam);
ret = MXL862XX_API_WRITE(priv, MXL862XX_MAC_TABLEENTRYADD, aparam);
ret = MXL862XX_API_WRITE(ds->priv, MXL862XX_COMMON_CFGSET, param);
ret = MXL862XX_API_WRITE(priv, MXL862XX_STP_PORTCFGSET, param);
return MXL862XX_API_WRITE(priv, INT_GPHY_WRITE, param);
ret = MXL862XX_API_WRITE(priv, MXL862XX_BRIDGE_CONFIGSET, bridge_config);
ret = MXL862XX_API_WRITE(priv, MXL862XX_QOS_METERCFGSET, meter);
ret = MXL862XX_API_WRITE(priv, MXL862XX_COMMON_REGISTERMOD, reg);
ret = MXL862XX_API_WRITE(priv, MXL862XX_COMMON_REGISTERMOD, reg);
return MXL862XX_API_WRITE(priv, MXL862XX_COMMON_REGISTERMOD, reg);
return MXL862XX_API_WRITE(priv, MXL862XX_BRIDGEPORT_CONFIGSET,
return MXL862XX_API_WRITE(priv, MXL862XX_VLANFILTER_SET, cfg);
ret = MXL862XX_API_WRITE(priv, MXL862XX_BRIDGE_FREE, br_alloc);
ret = MXL862XX_API_WRITE(ds->priv, MXL862XX_COMMON_REGISTERMOD, sdma);
return MXL862XX_API_WRITE(ds->priv, MXL862XX_COMMON_REGISTERMOD, fdma);
if (MXL862XX_API_WRITE(ds->priv, MXL862XX_MAC_TABLECLEARCOND, param))
return MXL862XX_API_WRITE(ds->priv, MXL862XX_CTP_PORTASSIGNMENTSET,
return MXL862XX_API_WRITE(ds->priv, MXL862XX_SS_SPTAG_SET, tag);
return MXL862XX_API_WRITE(priv, MXL862XX_EXTENDEDVLAN_SET, cfg);
return MXL862XX_API_WRITE(priv, MXL862XX_EXTENDEDVLAN_SET, cfg);
return MXL862XX_API_WRITE(priv, MXL862XX_VLANFILTER_SET, cfg);