MVPP22_XLG_CTRL0_REG
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
writel(val, port->base + MVPP22_XLG_CTRL0_REG);