drivers/clk/mediatek/clk-mt7988-infracfg.c

59

MUX_CLR_SET(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

61

MUX_CLR_SET(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

63

MUX_CLR_SET(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

65

MUX_CLR_SET(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

67

MUX_CLR_SET(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

69

MUX_CLR_SET(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

71

MUX_CLR_SET(CLK_INFRA_PWM_SEL, "infra_pwm_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

73

MUX_CLR_SET(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

75

MUX_CLR_SET(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

77

MUX_CLR_SET(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

79

MUX_CLR_SET(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

81

MUX_CLR_SET(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

83

MUX_CLR_SET(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

85

MUX_CLR_SET(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

87

MUX_CLR_SET(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

90

MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

92

MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

94

MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",

drivers/clk/mediatek/clk-mt7988-infracfg.c

96

MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",

drivers/clk/mediatek/clk-mt8192.c

581

MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents,