MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK
reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;