MUX_SEL_DISP2
MUX_SEL_DISP2,
MUX_SEL_DISP2, 0, 1),
MUX_SEL_DISP2, 4, 1),
MUX_SEL_DISP2,
{ MUX_SEL_DISP2, 0 },
mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,