MUX_SEL_DISP1
MUX_SEL_DISP1,
MUX_SEL_DISP1, 0, 1),
MUX_SEL_DISP1, 4, 1),
MUX_SEL_DISP1, 8, 1),
MUX_SEL_DISP1, 16, 1),
MUX_SEL_DISP1, 20, 1),
MUX_SEL_DISP1, 24, 1),
MUX_SEL_DISP1, 28, 1),
MUX_SEL_DISP1,
{ MUX_SEL_DISP1, 0 },
mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
MUX_SEL_DISP1, 20, 1),
mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),