MUX_SEL_DISP0
MUX_SEL_DISP0,
MUX_SEL_DISP0, 0, 1),
MUX_SEL_DISP0, 4, 1),
MUX_SEL_DISP0, 8, 1),
MUX_SEL_DISP0, 16, 1),
MUX_SEL_DISP0, 20, 1),
MUX_SEL_DISP0, 24, 1),
MUX_SEL_DISP0, 28, 1),
MUX_SEL_DISP0,
{ MUX_SEL_DISP0, 0 },
MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,