Symbol: MUX_CLR_SET_UPD
drivers/clk/mediatek/clk-mt6735-topckgen.c
335
MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
drivers/clk/mediatek/clk-mt6735-topckgen.c
336
MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
drivers/clk/mediatek/clk-mt6735-topckgen.c
337
MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
drivers/clk/mediatek/clk-mt6735-topckgen.c
353
MUX_CLR_SET_UPD(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 0, 0),
drivers/clk/mediatek/clk-mt8192.c
582
MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
drivers/clk/mediatek/clk-mt8196-topckgen.c
617
MUX_CLR_SET_UPD(CLK_TOP_AXI, "axi",
drivers/clk/mediatek/clk-mt8196-topckgen.c
621
MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB, "mem_sub",
drivers/clk/mediatek/clk-mt8196-topckgen.c
625
MUX_CLR_SET_UPD(CLK_TOP_IO_NOC, "io_noc",
drivers/clk/mediatek/clk-mt8196-topckgen.c
629
MUX_CLR_SET_UPD(CLK_TOP_P_AXI, "p_axi",
drivers/clk/mediatek/clk-mt8196-topckgen.c
634
MUX_CLR_SET_UPD(CLK_TOP_UFS_PEXTP0_AXI, "ufs_pextp0_axi",
drivers/clk/mediatek/clk-mt8196-topckgen.c
638
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_AXI, "pextp1_usb_axi",
drivers/clk/mediatek/clk-mt8196-topckgen.c
642
MUX_CLR_SET_UPD(CLK_TOP_P_FMEM_SUB, "p_fmem_sub",
drivers/clk/mediatek/clk-mt8196-topckgen.c
646
MUX_CLR_SET_UPD(CLK_TOP_PEXPT0_MEM_SUB, "ufs_pexpt0_mem_sub",
drivers/clk/mediatek/clk-mt8196-topckgen.c
651
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_MEM_SUB, "pextp1_usb_mem_sub",
drivers/clk/mediatek/clk-mt8196-topckgen.c
655
MUX_CLR_SET_UPD(CLK_TOP_P_NOC, "p_noc",
drivers/clk/mediatek/clk-mt8196-topckgen.c
659
MUX_CLR_SET_UPD(CLK_TOP_EMI_N, "emi_n",
drivers/clk/mediatek/clk-mt8196-topckgen.c
663
MUX_CLR_SET_UPD(CLK_TOP_EMI_S, "emi_s",
drivers/clk/mediatek/clk-mt8196-topckgen.c
668
MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST, "ap2conn_host",
drivers/clk/mediatek/clk-mt8196-topckgen.c
672
MUX_CLR_SET_UPD(CLK_TOP_ATB, "atb",
drivers/clk/mediatek/clk-mt8196-topckgen.c
677
MUX_CLR_SET_UPD(CLK_TOP_CIRQ, "cirq",
drivers/clk/mediatek/clk-mt8196-topckgen.c
681
MUX_CLR_SET_UPD(CLK_TOP_PBUS_156M, "pbus_156m",
drivers/clk/mediatek/clk-mt8196-topckgen.c
686
MUX_CLR_SET_UPD(CLK_TOP_EFUSE, "efuse",
drivers/clk/mediatek/clk-mt8196-topckgen.c
690
MUX_CLR_SET_UPD(CLK_TOP_MCL3GIC, "mcu_l3gic",
drivers/clk/mediatek/clk-mt8196-topckgen.c
694
MUX_CLR_SET_UPD(CLK_TOP_MCINFRA, "mcu_infra",
drivers/clk/mediatek/clk-mt8196-topckgen.c
698
MUX_CLR_SET_UPD(CLK_TOP_DSP, "dsp",
drivers/clk/mediatek/clk-mt8196-topckgen.c
838
MUX_CLR_SET_UPD(CLK_TOP_MCUPM, "mcupm",
drivers/clk/mediatek/clk-mt8196-topckgen.c
864
MUX_CLR_SET_UPD(CLK_TOP_EMI_INTERFACE_546, "emi_interface_546",
drivers/clk/mediatek/clk-mt8196-topckgen.c
868
MUX_CLR_SET_UPD(CLK_TOP_SDF, "sdf",
drivers/clk/mediatek/clk-mt8196-topckgen.c
878
MUX_CLR_SET_UPD(CLK_TOP_DPSW_CMP_26M, "dpsw_cmp_26m",
drivers/clk/mediatek/clk-mt8196-topckgen.c
882
MUX_CLR_SET_UPD(CLK_TOP_SMAP, "smap",
drivers/clk/mediatek/clk-mt8196-topckgen.c
886
MUX_CLR_SET_UPD(CLK_TOP_SSR_PKA, "ssr_pka",
drivers/clk/mediatek/clk-mt8196-topckgen.c
890
MUX_CLR_SET_UPD(CLK_TOP_SSR_DMA, "ssr_dma",
drivers/clk/mediatek/clk-mt8196-topckgen.c
895
MUX_CLR_SET_UPD(CLK_TOP_SSR_KDF, "ssr_kdf",
drivers/clk/mediatek/clk-mt8196-topckgen.c
899
MUX_CLR_SET_UPD(CLK_TOP_SSR_RNG, "ssr_rng",
drivers/clk/mediatek/clk-mt8196-topckgen.c
903
MUX_CLR_SET_UPD(CLK_TOP_SPU0, "spu0",
drivers/clk/mediatek/clk-mt8196-topckgen.c
907
MUX_CLR_SET_UPD(CLK_TOP_SPU1, "spu1",
drivers/clk/mediatek/clk-mt8196-topckgen.c
912
MUX_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
432
MUX_CLR_SET_UPD(CLK_VLP_SCP_SPI, "vlp_scp_spi",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
436
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC, "vlp_scp_iic",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
440
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC_HS, "vlp_scp_iic_hs",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
445
MUX_CLR_SET_UPD(CLK_VLP_PWRAP_ULPOSC, "vlp_pwrap_ulposc",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
449
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_TIA_32K, "vlp_spmi_32k",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
453
MUX_CLR_SET_UPD(CLK_VLP_APXGPT_26M_B, "vlp_apxgpt_26m_b",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
457
MUX_CLR_SET_UPD(CLK_VLP_DPSW, "vlp_dpsw",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
462
MUX_CLR_SET_UPD(CLK_VLP_DPSW_CENTRAL, "vlp_dpsw_central",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
466
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_MST, "vlp_spmi_m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
470
MUX_CLR_SET_UPD(CLK_VLP_DVFSRC, "vlp_dvfsrc",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
479
MUX_CLR_SET_UPD(CLK_VLP_AXI_VLP, "vlp_axi_vlp",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
483
MUX_CLR_SET_UPD(CLK_VLP_SYSTIMER_26M, "vlp_systimer_26m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
487
MUX_CLR_SET_UPD(CLK_VLP_SSPM, "vlp_sspm",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
491
MUX_CLR_SET_UPD(CLK_VLP_SRCK, "vlp_srck",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
538
MUX_CLR_SET_UPD(CLK_VLP_SSPM_26M, "vlp_sspm_26m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
542
MUX_CLR_SET_UPD(CLK_VLP_ULPOSC_SSPM, "vlp_ulposc_sspm",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
546
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_26M, "vlp_vlp_pbus_26m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
551
MUX_CLR_SET_UPD(CLK_VLP_DEBUG_ERR_FLAG, "vlp_debug_err_flag",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
555
MUX_CLR_SET_UPD(CLK_VLP_DPMSRDMA, "vlp_dpmsrdma",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
559
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_156M, "vlp_vlp_pbus_156m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
563
MUX_CLR_SET_UPD(CLK_VLP_SPM, "vlp_spm",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
580
MUX_CLR_SET_UPD(CLK_VLP_NOC_VLP, "vlp_noc_vlp",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
606
MUX_CLR_SET_UPD(CLK_VLP_SPVLP_26M, "vlp_spvlp_26m",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
610
MUX_CLR_SET_UPD(CLK_VLP_SPU0_VLP, "vlp_spu0_vlp",
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
614
MUX_CLR_SET_UPD(CLK_VLP_SPU1_VLP, "vlp_spu1_vlp",