MT_WFDMA0_PCIE1
__mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
__mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0;
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
#define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118)
#define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c)
#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
#define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200)
#define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)