MT_WFDMA0
__mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
#define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
#define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
#define MT_MCU_CMD MT_WFDMA0(0x1f0)
#define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4)
#define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200)
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280)
#define MT_WFDMA0_INT_RX_PRI MT_WFDMA0(0x298)
#define MT_WFDMA0_INT_TX_PRI MT_WFDMA0(0x29c)
#define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
#define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600)
#define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604)
#define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
#define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
#define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
#define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
#define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
#define MT_WFDMA0_TX_RING15_EXT_CTRL MT_WFDMA0(0x63c)
#define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
#define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
#define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
#define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
#define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
#define MT_WFDMA0_RX_RING6_EXT_CTRL MT_WFDMA0(0x698)
#define MT_WFDMA0_RX_RING7_EXT_CTRL MT_WFDMA0(0x69c)
#define MT_TX_RING_BASE MT_WFDMA0(0x300)
#define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500)
__mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0;
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
#define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)
#define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
#define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268)
#define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c)
#define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270)
#define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c)
#define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
#define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
#define MT_INT_SOURCE_CSR MT_WFDMA0(0x200)
#define MT_INT_MASK_CSR MT_WFDMA0(0x204)
#define MT_MCU_CMD MT_WFDMA0(0x1f0)