MT_VEND_ADDR
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18));
val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i));
u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16));
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30);
mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17));
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16));
mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20));
mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val);
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x148),
mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000);
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16);
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff);
mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3));
mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0));
val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5),
mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL);
mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);