MTK_IOMMU_HAS_FLAG
if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
!MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
} else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
.ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
if (MTK_IOMMU_HAS_FLAG(data->plat_data, DL_WITH_MULTI_LARB)) {