MT8173_CLK_BCK1
clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
[MT8173_CLK_BCK1] = "bck1",
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);