arch/sh/kernel/cpu/sh4a/clock-sh7343.c

139

[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

140

[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

141

[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

142

[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

143

[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

144

[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

145

[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

146

[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

147

[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

148

[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

149

[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

150

[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

151

[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

152

[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

153

[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

154

[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

155

[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

156

[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

157

[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

158

[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

159

[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

160

[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

161

[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

142

[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

143

[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

144

[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

145

[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

146

[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

147

[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

148

[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

149

[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

150

[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

151

[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

152

[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

153

[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

154

[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

155

[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

156

[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

157

[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

158

[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

159

[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

160

[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

161

[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

162

[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

142

[HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

143

[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

144

[HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

145

[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

146

[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

147

[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

148

[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

149

[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

150

[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

143

[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

144

[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

145

[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

146

[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

147

[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

148

[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

149

[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

150

[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

151

[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

152

[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

153

[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

154

[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

155

[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

156

[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

157

[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

158

[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

159

[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

160

[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

161

[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

162

[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

163

[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

164

[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

165

[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

166

[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

167

[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

168

[HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

203

[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

204

[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

205

[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

206

[HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

207

[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

208

[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

209

[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

210

[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

211

[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

212

[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

213

[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

214

[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

215

[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

216

[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

217

[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

218

[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

219

[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

220

[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

221

[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

222

[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

223

[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

224

[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

225

[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

226

[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

227

[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

126

[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

127

[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

128

[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

129

[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

130

[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

131

[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

132

[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

133

[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

134

[MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

135

[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

136

[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

137

[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

138

[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

139

[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

140

[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

141

[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

142

[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

143

[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

85

[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

86

[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

100

[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

101

[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

102

[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

103

[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

104

[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

105

[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

106

[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

91

[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

92

[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

93

[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

94

[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

95

[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

96

[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

97

[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

98

[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

99

[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

100

[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

101

[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

102

[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

103

[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

104

[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

105

[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

106

[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

107

[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

108

[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

109

[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

110

[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

111

[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

112

[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

92

[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

93

[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

94

[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

95

[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

96

[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

97

[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

98

[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

99

[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

83

[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

84

[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

85

[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

86

[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

87

[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

88

[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

89

[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

90

[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

91

[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

arch/sh/kernel/cpu/sh4a/clock-shx3.c

92

[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),