arch/x86/kvm/svm/sev.c

4646

svm_disable_intercept_for_msr(vcpu, MSR_AMD64_SEV_ES_GHCB, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4647

svm_disable_intercept_for_msr(vcpu, MSR_EFER, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4648

svm_disable_intercept_for_msr(vcpu, MSR_IA32_CR_PAT, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4651

svm_set_intercept_for_msr(vcpu, MSR_TSC_AUX, MSR_TYPE_RW,

arch/x86/kvm/svm/sev.c

4670

svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

3066

svm_disable_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

741

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

742

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

743

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

744

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

747

svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

769

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

774

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

778

MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

782

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

784

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

786

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

788

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

795

svm_disable_intercept_for_msr(vcpu, MSR_STAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

796

svm_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

799

svm_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

800

svm_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

801

svm_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

802

svm_disable_intercept_for_msr(vcpu, MSR_LSTAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

803

svm_disable_intercept_for_msr(vcpu, MSR_CSTAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

804

svm_disable_intercept_for_msr(vcpu, MSR_SYSCALL_MASK, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

825

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

828

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

835

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

837

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

848

svm_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

849

svm_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

850

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

851

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

852

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

853

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/vmx/nested.c

700

nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_RW)

arch/x86/kvm/vmx/nested.c

828

MSR_IA32_U_CET, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

831

MSR_IA32_S_CET, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

834

MSR_IA32_PL0_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

837

MSR_IA32_PL1_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

840

MSR_IA32_PL2_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

843

MSR_IA32_PL3_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/pmu_intel.c

672

vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

673

vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

675

vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

678

vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

679

vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/vmx.c

2357

MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

2450

MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4182

vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4189

vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4199

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4200

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4201

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4202

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4204

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4205

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4238

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4239

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4244

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4246

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4251

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4254

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4258

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4260

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4262

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4274

vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4275

vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4276

vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4278

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4279

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4280

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4297

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_XFD, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4299

vmx_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4317

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4318

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4319

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4320

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4327

vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4328

vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, intercept);