MSR_IA32_APICBASE
if (rdmsrq_safe(MSR_IA32_APICBASE, &msr))
rdmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_IA32_APICBASE, l, h);
rdmsrq(MSR_IA32_APICBASE, msr);
wrmsrq(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
wrmsrq(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
rdmsrq(MSR_IA32_APICBASE, msr);
wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_IA32_APICBASE, l, h);
rdmsr(MSR_IA32_APICBASE, l, h);
wrmsr(MSR_IA32_APICBASE, l, h);
rdmsrq(MSR_IA32_APICBASE, msr);
case MSR_IA32_APICBASE:
return index == MSR_IA32_APICBASE || index == MSR_EFER ||
case MSR_IA32_APICBASE:
case MSR_IA32_APICBASE:
case MSR_IA32_APICBASE:
return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP;
wrmsr(MSR_IA32_APICBASE,
rdmsr(MSR_IA32_APICBASE) &
u64 val = rdmsr(MSR_IA32_APICBASE);
wrmsr(MSR_IA32_APICBASE,
rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE);
wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE);
wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) |
vcpu_set_msr(vcpus[i], MSR_IA32_APICBASE, LAPIC_X2APIC);
vcpu_set_msr(vcpuN, MSR_IA32_APICBASE, LAPIC_X2APIC);
vcpu_set_msr(vcpuN, MSR_IA32_APICBASE, LAPIC_DISABLED);
u64 apicbase = rdmsr(MSR_IA32_APICBASE);
wrmsr(MSR_IA32_APICBASE, apicbase | X2APIC_ENABLE);
u64 msr = rdmsr(MSR_IA32_APICBASE);
GUEST_ASSERT(rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_EXTD);
GUEST_ASSERT(!(rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_EXTD));
u64 msr = rdmsr(MSR_IA32_APICBASE);
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
apic_base = vcpu_get_msr(vcpus[i], MSR_IA32_APICBASE);
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);