AST_IO_VGACRI
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
u8 vgacrd0 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd0);
vgacrd1 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd1);
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc8, addr0);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc9, addr1);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xca, addr2);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc2, x_offset);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc3, y_offset);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc4, x0);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc5, x1);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc6, y0);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xc7, y1);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xcb, mask, vgacrcb);
val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01;
val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01;
val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01;
val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01;
val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01;
val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01;
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf1, ujcrb7);
jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x04);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf4, ujcrb7);
jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x01);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE, 0x00);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe4, vgacre4);
vgacrd7 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd7);
vgacrd6 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd6);
ediddata[0] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd8);
ediddata[1] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd9);
ediddata[2] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xda);
ediddata[3] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xdb);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE,
u8 vgacrd1 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd1);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5,
u8 vgacre3 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xe3);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe3, (u8)~AST_IO_VGACRE3_DP_PHY_SLEEP,
vgacrdc = ast_get_index_reg(ast, AST_IO_VGACRI, 0xdc);
vgacrdf = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xdf,
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe3, (u8)~AST_IO_VGACRE3_DP_VIDEO_ENABLE,
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe0, vgacre0);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe1, vgacre1);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe2, vgacre2);
if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, AST_IO_VGACRDF_HPD))
if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, AST_IO_VGACRDC_LINK_SUCCESS))
waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data);
tmp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd3, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, 0x00);
jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
ast_set_index_reg(ast, AST_IO_VGACRI, 0x99, jreg);
jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00);
vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack);
waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x40);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x00);
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED);
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1,
__ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD);
vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0);
vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1);
vgacraa = ast_get_index_reg(ast, AST_IO_VGACRI, 0xaa);
vgacr99 = ast_get_index_reg(ast, AST_IO_VGACRI, 0x99);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, vgacr8c);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, vgacr92);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x8d, refresh_rate_index & 0xff);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x8e, mode_id & 0xff);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x96, adjusted_mode->crtc_vdisplay);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x97, adjusted_mode->crtc_vdisplay >> 8);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00);
ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x00, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x01, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x02, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x03, 0xE0, (temp & 0x1f));
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x04, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAC, 0x00, jregAC);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAD, 0x00, jregAD);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x02);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x06, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x10, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x70, temp & 0xf);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x12, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x15, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x16, 0x00, temp);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x07, 0x00, jreg07);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x09, 0xdf, jreg09);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAE, 0x00, (jregAE | 0x80));
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x80);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x00);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x80);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x13, (offset & 0xff));
ast_set_index_reg(ast, AST_IO_VGACRI, 0xb0, (offset >> 8) & 0x3f);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc0, 0x00, clk_info->param1);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc1, 0x00, clk_info->param2);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xbb, 0x0f,
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, vgacra0);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, vgacra3);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, vgacra8);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, vgacra7);
ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, vgacra6);
ast_set_index_reg(ast, AST_IO_VGACRI, 0x0d, (u8)(addr & 0xff));
ast_set_index_reg(ast, AST_IO_VGACRI, 0x0c, (u8)((addr >> 8) & 0xff));
ast_set_index_reg(ast, AST_IO_VGACRI, 0xaf, (u8)((addr >> 16) & 0xff));
ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x06);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6);
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17);