arch/x86/kvm/svm/svm.c

680

if (type & MSR_TYPE_W) {

arch/x86/kvm/svm/svm.c

788

svm_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/svm/svm.c

792

svm_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/nested.c

580

if (type & MSR_TYPE_W && !vmx_test_msr_bitmap_write(msr_bitmap_l1, msr))

arch/x86/kvm/vmx/nested.c

619

if (types & MSR_TYPE_W)

arch/x86/kvm/vmx/nested.c

632

nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_W)

arch/x86/kvm/vmx/nested.c

729

MSR_TYPE_R | MSR_TYPE_W);

arch/x86/kvm/vmx/nested.c

735

MSR_TYPE_W);

arch/x86/kvm/vmx/nested.c

739

MSR_TYPE_W);

arch/x86/kvm/vmx/vmx.c

4203

if (type & MSR_TYPE_W) {

arch/x86/kvm/vmx/vmx.c

4264

vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);

arch/x86/kvm/vmx/vmx.c

4265

vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);

arch/x86/kvm/vmx/vmx.c

4385

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/vmx.c

4389

vmx_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/x86.c

1957

return kvm_do_msr_access(vcpu, index, &data, host_initiated, MSR_TYPE_W,

arch/x86/kvm/x86.c

3881

BUILD_BUG_ON(access != MSR_TYPE_R && access != MSR_TYPE_W);

arch/x86/kvm/x86.c

3896

kvm_access_xstate_msr(vcpu, msr_info, MSR_TYPE_W);

arch/x86/kvm/x86.c

524

const char *op = rw == MSR_TYPE_W ? "wrmsr" : "rdmsr";

arch/x86/kvm/x86.c

527

BUILD_BUG_ON(rw != MSR_TYPE_R && rw != MSR_TYPE_W);

arch/x86/kvm/x86.h

662

MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W,