arch/x86/kvm/svm/avic.c

156

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/sev.c

4557

svm_disable_intercept_for_msr(vcpu, MSR_AMD64_SEV_ES_GHCB, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4558

svm_disable_intercept_for_msr(vcpu, MSR_EFER, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4559

svm_disable_intercept_for_msr(vcpu, MSR_IA32_CR_PAT, MSR_TYPE_RW);

arch/x86/kvm/svm/sev.c

4562

svm_set_intercept_for_msr(vcpu, MSR_TSC_AUX, MSR_TYPE_RW,

arch/x86/kvm/svm/sev.c

4581

svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

2974

svm_disable_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

718

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

719

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTBRANCHTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

720

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTFROMIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

721

svm_set_intercept_for_msr(vcpu, MSR_IA32_LASTINTTOIP, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

724

svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

746

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

751

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

755

MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

759

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

761

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

763

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

765

MSR_TYPE_RW, intercept);

arch/x86/kvm/svm/svm.c

772

svm_disable_intercept_for_msr(vcpu, MSR_STAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

773

svm_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

776

svm_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

777

svm_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

778

svm_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

779

svm_disable_intercept_for_msr(vcpu, MSR_LSTAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

780

svm_disable_intercept_for_msr(vcpu, MSR_CSTAR, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

781

svm_disable_intercept_for_msr(vcpu, MSR_SYSCALL_MASK, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

802

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

805

svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

812

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

814

svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW,

arch/x86/kvm/svm/svm.c

825

svm_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

826

svm_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

827

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

828

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

829

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/svm/svm.c

830

svm_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, !shstk_enabled);

arch/x86/kvm/vmx/nested.c

635

nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_RW)

arch/x86/kvm/vmx/nested.c

763

MSR_IA32_U_CET, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

766

MSR_IA32_S_CET, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

769

MSR_IA32_PL0_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

772

MSR_IA32_PL1_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

775

MSR_IA32_PL2_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/nested.c

778

MSR_IA32_PL3_SSP, MSR_TYPE_RW);

arch/x86/kvm/vmx/pmu_intel.c

661

vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

662

vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

664

vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

667

vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

668

vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/vmx.c

2368

MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

2461

MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4259

vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4263

vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4267

vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4277

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4278

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4279

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4280

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4282

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4283

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4316

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4317

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4322

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4324

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4329

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4332

MSR_TYPE_RW, true);

arch/x86/kvm/vmx/vmx.c

4336

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4338

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4340

MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4352

vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4353

vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4354

vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4356

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4357

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4358

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4375

vmx_disable_intercept_for_msr(vcpu, MSR_IA32_XFD, MSR_TYPE_RW);

arch/x86/kvm/vmx/vmx.c

4377

vmx_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4395

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4396

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4397

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4398

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4405

vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4406

vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, intercept);