MSR_TYPE_R
svm_set_intercept_for_msr(vcpu, MSR_AMD64_GUEST_TSC_FREQ, MSR_TYPE_R,
if (type & MSR_TYPE_R) {
svm_disable_intercept_for_msr(vcpu, MSR_IA32_APERF, MSR_TYPE_R);
svm_disable_intercept_for_msr(vcpu, MSR_IA32_MPERF, MSR_TYPE_R);
if (type & MSR_TYPE_R && !vmx_test_msr_bitmap_read(msr_bitmap_l1, msr))
if (types & MSR_TYPE_R)
nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_R)
MSR_TYPE_R | MSR_TYPE_W);
MSR_IA32_APERF, MSR_TYPE_R);
MSR_IA32_MPERF, MSR_TYPE_R);
if (type & MSR_TYPE_R) {
vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_IA32_APERF, MSR_TYPE_R);
vmx_disable_intercept_for_msr(vcpu, MSR_IA32_MPERF, MSR_TYPE_R);
vmx_set_intercept_for_msr(vcpu, MSR_IA32_XFD_ERR, MSR_TYPE_R,
return kvm_do_msr_access(vcpu, index, data, true, MSR_TYPE_R,
return kvm_do_msr_access(vcpu, index, data, host_initiated, MSR_TYPE_R,
BUILD_BUG_ON(access != MSR_TYPE_R && access != MSR_TYPE_W);
if (access == MSR_TYPE_R)
kvm_access_xstate_msr(vcpu, msr_info, MSR_TYPE_R);
BUILD_BUG_ON(rw != MSR_TYPE_R && rw != MSR_TYPE_W);
if (ret && rw == MSR_TYPE_R)
MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W,