arch/x86/events/intel/p6.c

146

rdmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/p6.c

148

wrmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/p6.c

156

rdmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/p6.c

158

wrmsrq(MSR_P6_EVNTSEL0, val);

arch/x86/events/intel/p6.c

213

.eventsel = MSR_P6_EVNTSEL0,

arch/x86/kernel/cpu/perfctr-watchdog.c

93

return msr - MSR_P6_EVNTSEL0;

arch/x86/kvm/vmx/pmu_intel.c

196

get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||

arch/x86/kvm/vmx/pmu_intel.c

211

pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);

arch/x86/kvm/vmx/pmu_intel.c

359

} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {

arch/x86/kvm/vmx/pmu_intel.c

424

} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {

arch/x86/kvm/vmx/pmu_intel.c

846

.GP_EVENTSEL_BASE = MSR_P6_EVNTSEL0,

arch/x86/kvm/x86.c

4210

case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:

arch/x86/kvm/x86.c

4392

case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:

arch/x86/xen/pmu.c

179

if ((msr_index >= MSR_P6_EVNTSEL0) &&

arch/x86/xen/pmu.c

180

(msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) {

arch/x86/xen/pmu.c

181

*index = msr_index - MSR_P6_EVNTSEL0;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

296

wrmsr(MSR_P6_EVNTSEL0 + i, 0);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

301

MSR_P6_EVNTSEL0 + i, eventsel);

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

106

check_msr(MSR_P6_EVNTSEL0, 0xffff);

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

112

wrmsr(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

444

wrmsr(MSR_P6_EVNTSEL0 + 0, ARCH_PERFMON_EVENTSEL_ENABLE |

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

446

wrmsr(MSR_P6_EVNTSEL0 + 1, ARCH_PERFMON_EVENTSEL_ENABLE |

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

448

wrmsr(MSR_P6_EVNTSEL0 + 2, ARCH_PERFMON_EVENTSEL_ENABLE |